cxa2153s Sony Electronics, cxa2153s Datasheet
cxa2153s
Available stocks
Related parts for cxa2153s
cxa2153s Summary of contents
Page 1
... Preamplifier for High Resolution Computer Display Description The CXA2153S is a bipolar IC developed for high resolution computer displays. Features • Built-in wide-band amplifier: 180MHz@–3dB (Typ.) • Input dynamic range: 1.0Vp-p (Typ.) • High gain preamplifier (15dB) • and B incorporated in a single package ...
Page 2
... Block Diagram 12 SYNCIN 4 VREF R_BKG 21 G_BKG 20 B_BKG – 2 – CXA2153S 25 8 OSD_BLK 9 OSD_R 10 OSD_G 11 OSD_B 15 VDET 13 CLP 6 ...
Page 3
... Pin Configuration RIN GIN SYNCIN GND BIN ABL OSD_BLK OSD_R OSD_G 10 OSD_B 11 SYNCOUT 12 CLP 13 BLK 14 VDET – 3 – CXA2153S ROUT 28 GND_R 27 GOUT GND_G 26 25 BOUT 24 GND_B 23 VREF R_BKG 20 G_BKG 19 B_BKG SCL 16 ...
Page 4
... 500 2k 500 10k 7 20k 10k 30k – 4 – CXA2153S Description RGB signal inputs. Input via the capacitor. 5V power supply. Sync-on-green signal input. Input via the capacitor. GND ABL input. OSD_BLK control input. VILMAX = 0.8V VIHMIN = 2.8V ...
Page 5
... 30k 30k – 5 – CXA2153S Description OSD control input. VILMAX = 0.8V VIHMIN = 2.8V Sync separator output of Sync- on-green signal bus SOG off: Output at 0. Typ.: High = 4.2V Low = 0.2V (positive polarity) Clamp pulse (positive polarity) input. VILMAX = 0.8V VIHMIN = 2.8V Blanking pulse input ...
Page 6
... 10k VREG VREG V CC 100 100 1k – 6 – CXA2153S Description Video detector output bus VDET off: Output bus standard SDA (serial data) input/output. VILMAX = 1.5V VIHMIN = 3.5V VOLMAX = 0. bus standard SCL (serial clock) input. VILMAX = 1.5V VIHMIN = 3 ...
Page 7
... GND_G 0V 24 GND_B 29 ROUT 27 GOUT 25 BOUT Equivalent circuit Band Gap V 12 VREG – 7 – CXA2153S Description 9V regulator. Connect with Vcc12 via a resistor of around 220 . It cannot be used as an external power supply. GNDs R, G and B signal outputs. ...
Page 8
... Output voltage maximum (5.5V) Controls Pin 20 (G BACKGROUND) output voltage. 0: Output voltage minimum (1.5V) 255: Output voltage maximum (5.5V) Controls Pin 19 (B BACKGROUND) output voltage. 0: Output voltage minimum (1.5V) 255: Output voltage maximum (5.5V) – 8 – CXA2153S BIT 2 BIT 1 BIT 0 SHP GAIN GAMMA2 OFF ...
Page 9
... F: Gain maximum (6dB) Amplitude at SHP OFF is assumed to be 0dB. Controls the polarity of the correction at GAMMA1. 0: – correction 1: + correction Controls the gain of the inflection point 1 (15 IRE) at GAMMA IRE correction 3: 9 IRE correction Controls the polarity of the correction at GAMMA2. 0: – correction 1: + correction – 9 – CXA2153S ...
Page 10
... Controls the sync separator output. 0: Output on 1: Output off Controls the gamma function operation. 0: Gamma on 1: Gamma off Controls the VBLK synchronous DAC refresh function. The operation of this function is set to OFF when the power is turned on. 0: Function operation on 1: Function operation off – 10 – CXA2153S ...
Page 11
... HD t 1.3 LOW t 0.6 HIGH t ; STA 0 DAT DAT 100 SU t — — STO 0.6 SU – 11 – CXA2153S Max. Unit — 5.0 V — 1.5 V — 0.4 V — 400 kHz — — µs — — µs — — µs — — µs — — µs — ...
Page 12
... Measure the level of the output signal amplitude Vout when a 0.7Vp-p video signal is input. GCONT1: Contrast = DRIVE = FF GCONT2: Contrast = 00/DRIVE = FF Input signal 0.7Vp-p Calculate the difference in the data obtained in No.5 and No.6 between the channels. – 12 – CXA2153S Min. Typ. Max. Unit ...
Page 13
... VBRT2: Brightness = FF RGB output signal Black level GND Calculate the difference in the data obtained in No.11 between the channels. Measure the BLK level of the output signal when a BLK pulse is input. BLK level GND – 13 – CXA2153S Min. Typ. Max. Unit –100 0 120 mVp-p 4 4.57 5.15 Vp-p –330 ...
Page 14
... RGB input 0.7Vp-p Vth = 50% Rise Fall Delay Delay Vth = 50% VDET output VDET output VDET-Lo VDET-Hi GND – 14 – CXA2153S Min. Typ. Max. Unit 6.5 8 6.5 8.8 11 3.9 4 — V — 0.2 0.45 0.24 — ...
Page 15
... RGB inputs, and measure the output amplitude. GAM1: GAMMA1 = 3/POL1 = 1, Vin = 0.105Vp-p GAM2: GAMMA1 = 3/POL1 = 0, Vin = 0.105Vp-p GAM3: GAMMA2 = F/POL2 = 1, Vin = 0.42Vp-p GAM4: GAMMA2 = F/POL2 = 0, Vin = 0.42Vp-p (CONTRAST: 7F/DRIVE: FF/ABL: 5V) – 15 – CXA2153S Min. Typ. Max. Unit 1.25 1.45 1.67 V 5.45 5.7 5.95 3.35 3.8 4.4 Vp-p 0 ...
Page 16
... BRIGHTNESS Control Characteristics 3.0 2.5 2.0 1.5 1.0 0 256 RGB BKG/G2 Control Characteristics 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1 – 16 – CXA2153S 64 96 128 160 192 224 256 OSD GAIN data 64 96 128 160 192 224 256 BRIGHTNESS data 64 96 128 160 192 224 256 Control data ...
Page 17
... Frequency Characteristic –2 – 100 Input frequency [MHz] – 17 – CXA2153S 1000 ...
Page 18
... OSD_R OSD_G R_BKG 21 11 OSD_B G_BKG 20 12 SYNCOUT B_BKG CLP G2 14 BLK SCL 17 15 VDET SDA 16 – 18 – CXA2153S 47 F 12V Rch Output 0.1 F Gch Output Bch Output 0 220 12V 0.1 F DAC Output 220 Bus 220 ...
Page 19
... OSD_R OSD_G R_BKG OSD_B G_BKG 12 19 SYNCOUT B_BKG 13 18 CLP BLK SCL 15 16 VDET SDA – 19 – CXA2153S 47 F 12V Rch Output 0.1 F Gch Output Bch Output 0 VREF 220 12V 0.1 F DAC Output 220 Bus 220 ...
Page 20
... OSD_R OSD_G R_BKG 21 11 OSD_B G_BKG 20 12 SYNCOUT B_BKG CLP G2 14 BLK SCL 17 15 VDET SDA 16 – 20 – CXA2153S 47 F 12V 0.1 F Rch Output Gch Output Bch Output 0 220 12V 0.1 F DAC Output 220 Bus 220 ...
Page 21
... 50ns The output level when RIN = GIN = BIN = 0.7Vp set to 100%. 100ns ( GAMMA2 +20 [IRE] 100 [IRE] 0 100 [IRE] – 21 – CXA2153S 2 C bus data 2 C bus data transmission from the –20 [IRE] 100 [IRE] 60 [IRE] 100 [IRE] ...
Page 22
... The DAC is not rewritten while the bus data in the VBLK period is being transmitted. The transmitted data is held bus data transmission from the microcomputer is 12 OFF) CC – 22 – CXA2153S Data group (3) The data in (3) written. The data in (2) written, if (3) is not transmitted bus data is held ...
Page 23
... When not using the sync separation function, connect the Sync In pin to GND through a capacitor, and set SOG_OFF = 1 (bus setting). 11. When there is no clamp pulse input to Pin 13 (CLP), the output potential rises. Always input a clamp pulse. 12V, and off in the order of 12V – 23 – CXA2153S 5V. (Be sure to observe this ...
Page 24
... JEDEC CODE 30PIN SDIP (PLASTIC 1.778 0.5 0.1 0.9 0.15 PACKAGE STRUCTURE MOLDING COMPOUND LEAD TREATMENT LEAD MATERIAL PACKAGE MASS – 24 – CXA2153S Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 1.8g Sony Corporation ...