IC 2INPUT OR GATE QUAD 14SOIC

HEF4071BT,653

Manufacturer Part NumberHEF4071BT,653
DescriptionIC 2INPUT OR GATE QUAD 14SOIC
ManufacturerNXP Semiconductors
Series4000B
HEF4071BT,653 datasheet
 

Specifications of HEF4071BT,653

Number Of Circuits4Package / Case14-SOIC (3.9mm Width), 14-SOL
Logic TypeOR GateNumber Of Inputs2
Current - Output High, Low2.4mA, 2.4mAVoltage - Supply4.5 V ~ 15.5 V
Operating Temperature-40°C ~ 125°CMounting TypeSurface Mount
ProductORLogic FamilyHEF4000
High Level Output Current- 3.6 mALow Level Output Current3.6 mA
Propagation Delay Time20 nsSupply Voltage (max)15.5 V
Supply Voltage (min)3 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names933373020653
HEF4071BTD-T
HEF4071BTD-T
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HEF4071B
Quad 2-input OR gate
Rev. 06 — 1 December 2009
1. General description
The HEF4071B is a quad 2-input OR gate. The outputs are fully buffered for highest noise
immunity and pattern insensitivity to output impedance variations.
It operates over a recommended V
(usually ground). Unused inputs must be connected to V
It is also suitable for use over both the industrial (−40 °C to +85 °C) and automotive
(−40 °C to +125 °C) temperature ranges.
2. Features
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Inputs and outputs are protected against electrostatic effects
Operates across the automotive temperature range from −40 °C to +125 °C
Complies with JEDEC standard JESD 13-B
3. Applications
Automotive and industrial
4. Ordering information
Table 1.
Ordering information
°
All types operate from
40
C to +125
Type number
Package
Name
HEF4071BP
DIP14
HEF4071BT
SO14
power supply range of 3 V to 15 V referenced to V
DD
°
C.
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads; body width 3.9 mm
Product data sheet
SS
, V
, or another input.
DD
SS
Version
SOT27-1
SOT108-1

HEF4071BT,653 Summary of contents

  • Page 1

    HEF4071B Quad 2-input OR gate Rev. 06 — 1 December 2009 1. General description The HEF4071B is a quad 2-input OR gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations. It operates ...

  • Page 2

    ... NXP Semiconductors 5. Functional diagram 001aaj110 Fig 1. Functional diagram 6. Pinning information 6.1 Pinning Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin 10 HEF4071B_6 Product data sheet Fig 2. Logic diagram (one gate) HEF4071B 001aaj107 Description input input output ground (0 V) supply voltage Rev. 06 — ...

  • Page 3

    ... NXP Semiconductors 7. Functional description [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V Symbol Parameter V supply voltage DD I input clamping current IK V input voltage ...

  • Page 4

    ... NXP Semiconductors 10. Static characteristics Table 6. Static characteristics unless otherwise specified Symbol Parameter Conditions |I | < 1 μA V HIGH-level IH O input voltage |I | < 1 μA V LOW-level IL O input voltage |I | < 1 μA V HIGH-level OH O output voltage |I | < 1 μA V LOW-level OL O output voltage I HIGH-level output current ...

  • Page 5

    ... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics ° waveforms see Figure amb Symbol Parameter Conditions t HIGH to LOW PHL propagation delay t LOW to HIGH PLH propagation delay t transition time t [1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (C ...

  • Page 6

    ... NXP Semiconductors Table 9. Measurement points Supply voltage Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test load capacitance including jig and probe capacitance termination resistance should be equal to the output impedance Z T Fig 5. Test circuit Table 10. Test data Supply voltage ...

  • Page 7

    ... NXP Semiconductors 13. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. 1.73 mm 4.2 0.51 3.2 1.13 0.068 inches 0.17 0.02 0.13 0.044 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

  • Page 8

    ... NXP Semiconductors SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

  • Page 9

    ... NXP Semiconductors 14. Revision history Table 11. Revision history Document ID Release date HEF4071B_6 20091201 • Modifications: Section 9 “Recommended operating conditions” HEF4071B_5 20090728 HEF4071B_4 20081128 HEF4071B_CNV_3 19950101 HEF4071B_CNV_2 19950101 HEF4071B_6 Product data sheet Data sheet status Change notice Product data sheet - Δt/ΔV values updated. ...

  • Page 10

    ... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

  • Page 11

    ... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 14 Revision history ...