lc7940kd Sanyo Semiconductor Corporation, lc7940kd Datasheet
lc7940kd
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lc7940kd Summary of contents
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... LC7941KDR Overview The LC7940KD and LC7941KDR are segment driver LSIs for driving large, dot-matrix LCD displays. They read 4-bit parallel or serial input, display data from a controller into an 80-bit latch, and then generate LCD drive signals corresponding to that data. The LC7940KD and LC7941KDR feature mirror-image pin assignments, allowing them to be used together to increase component density ...
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... Package Dimensions unit: mm (typ) 3180 [LC7940KD] 23.2 20.0 0.575 0.65 0 100 1 21.6 SANYO : QIP100D(14X20) Package Dimensions unit: mm (typ) 3329 [LC7941KDR] 23.2 20 100 1 0.3 0.65 (0.58) SANYO : QIP100DR(14X20) LC7940KD / LC7941KDR 1.6 0. 2.15 0 0.15 No.A0573-2/13 ...
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... P/S 96 DISPOFF CDO 99 NC 100 LC7940KD / LC7941KDR LC7940KD LC7941KDR O50 50 49 O49 48 O48 47 O47 46 O46 O45 45 44 O44 43 O43 42 O42 ...
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... SDI 4 bits DI3 Data Bus DI2 Interface DI1 SER/PAR P/S Control CDI CP LOAD LC7940KD / LC7941KDR 4 Level LCD Drive Circuit (80 bits) 80 Level Shifter (80 bits) 80 2nd Latch (80 bits) 80 1st Latch (80 bits) 20 Address Decoder Address Counter (7bits) Chip Disable & Latch Control V DD ...
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... 100 NC LC7940KD / LC7941KDR I/O Supply LCD panel drive voltage supplies the logic supply the LCD supply. Supply LCD panel drive voltage supplies V1 and V EE are selected levels. V3 and V4 are not-selected levels. I Display data input clock (falling edge trigger). ...
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... When the power is turned off, either the LCD drive system power must be turned off before the logic system power, or else both must be turned off at the same time. LC7940KD / LC7941KDR Symbol Conditions ...
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... SETUP 0.8V DD SDI DI1 CL(1) LOAD CDO LC7940KD / LC7941KDR Conditions LOAD, CP, CDI, P/S, DI1 to DI3, SDI, M, and DISPOFF LOAD, CP, CDI, P/S, DI1 to DI3, SDI, M, and DISPOFF -400µA: CDO 400µA: CDO 18V 0.25V *4 CDI = 18V ...
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... Application Notes LCD Panel1 LC7940KD / LC7941KDR 159 160 161 239 240 No.A0573-8/13 ...
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... Application Notes LCD Panel2 LC7940KD / LC7941KDR No.A0573-9/13 ...
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... The LC7942KD chips are cascaded by connecting DIO64 on chip 1 to DIO1 on chip 2. For a 100-bit shift register, O37 to O64 on chip 2 are left open. (2) The LC7940KD (or LC7941KDR) chips are cascaded by connecting CDO on chip 1 to CDI on chip 2, and CDO on chip 2 to CDI on chip 3. CDI on chip 1 is tied to GND, and CDO on chop 3 is not used. ...
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... M #1 DIO1 LOAD O1 1 1,2 1,80 2,80 O80 O1 2,81 1,81 #2 O80 1,160 2,160 O1 2,161 1,161 #3 O80 1,240 2,240 LC7940KD / LC7941KDR ∼ ∼ 1,79 1,80 1,81 Chip 2 data read ∼ ∼ 1,239 1,240 2,1 2nd line data read ∼ 2,1 98,1 99,1 100,1 ∼ 98,2 99,2 100,2 2,2 ∼ 98,80 99,80 100,80 ∼ ...
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... If this timing data is sent, data elements (m, 229), (m, 230), (m+1, 229),(m+1, 230)… will not appear in the output (O69 and O70 on chip 3). This is because the LC7940KD (or LC7941KDR) converts serial/parallel data in 4-bit units, which also decrease power dissipation. For data that is not a multiple of 4, like 230, the following scheme is used. ...
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... LC7940KD / LC7941KDR Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment ...