sm8211m Nippon Precision Circuits Inc, (NPC), sm8211m Datasheet

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sm8211m

Manufacturer Part Number
sm8211m
Description
Pocsag Decoder For Pagers
Manufacturer
Nippon Precision Circuits Inc, (NPC)
Datasheet

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OVERVIEW
The SM8211M is a POCSAG-standard (Post Office
Code Standardization Advisory Group) signal pro-
cessor LSI, which conforms to CCIR recommenda-
tion 584 concerning standard international wireless
calling codes.
The SM8211M supports call messages in either tone,
numerical or character outputs at signal speeds of
512 bps or 1200 bps using a 76.8 kHz system clock,
or 2400 bps using a double-speed 153.6 kHz system
clock. Note that output timing values for 2400 bps
mode operation are not shown in this datasheet, but
can be obtained by halving the values for 1200 bps
mode operation.
CMOS structure and low-voltage operation realize
low power dissipation, plus an intermittent-duty
receive method (battery-saving function) reduces
battery consumption.
The SM8211M is available in 20-pin SSOPs.
FEATURES
NIPPON PRECISION CIRCUITS INC.
Conforms to POCSAG standard for pagers
512 or 1200 bps signal speed
Supports tone, numeric or character call messages
Battery-saving function for low battery consump-
tion
BS1 (RF control main output signal) and BS3
(PLL setup signal) 60-step setup time setting—for
BS3, 50.8 ms (max) at 1200 bps and 119.1 ms
(max) at 512 bps
Note that (BS3 setup time)
should be set to 2.
BS2 (RF DC-level adjustment signal) before/dur-
ing reception selectable adjustment timing
6 addresses
addresses)
1-bit and 2-bit burst error auto-correction function
(messages only)
25 to 75% duty factor signal coverage (during pre-
amble detection)
8 rate error detection condition settings
8 receive mode settings
76.8 or 153.6 kHz system clock (crystal oscillator
or external clock input)
Built-in oscillator capacitor
4 sub-addresses (total of 24
(BS1 setup time)
PINOUT
PACKAGE DIMENSIONS
Built-in input signal filter, with filter ON/OFF and
4 selectable filter characteristics
1.2 to 3.5 V (76.8 kHz system clock) or 2.0 to 3.5
V (153.6 kHz system clock) operating supply volt-
age
Molybdenum-gate CMOS process realizes low
power dissipation
20-pin SSOP
POCSAG Decoder For Pagers
TX-DATA
TX-CLK
BREAK
TEST1
TEST2
0.68 0.12
XVDD
2.35
VDD
BS1
BS2
BS3
7.20 0.05
7.40max
0.30 0.15
10
1
2
3
4
5
6
7
8
9
NIPPON PRECISION CIRCUITS—1
0.65 0.12
0.20 0.05
20
19
18
17
16
15
14
13
12
11
SM8211M
XTN
XT
SYN-VAL
RX-CLK
ADD-DET
VSS
SIG-IN
BACKUP
RX-DATA
RST
4
4

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sm8211m Summary of contents

Page 1

... LSI, which conforms to CCIR recommenda- tion 584 concerning standard international wireless calling codes. The SM8211M supports call messages in either tone, numerical or character outputs at signal speeds of 512 bps or 1200 bps using a 76.8 kHz system clock, or 2400 bps using a double-speed 153.6 kHz system clock ...

Page 2

... O 17 RX-CLK O 18 SYN-VAL XTN O I:Input O:Output SM8211M BACKUP BREAK BS1 BS2 Timing control Flag register Data comparator Preamble pattern Sync code Idle code Digital PLL Error correction TEST1 TEST2 Oscillator circuit supply pin. Capacitor connected between XVDD and VSS. ...

Page 3

... HIGH-level output voltage (all outputs except XTN) LOW-level output voltage (all outputs except XTN) Input leakage current (all inputs except XT) Standby supply current I 1. The consumption current is slightly higher when RST is going LOW. SM8211M Symbol stg ...

Page 4

... RX-CLK pulse cycle 1 RX-CLK pulsewidth 1 RX-DATA lead time 1 RX-DATA hold time 1. Internal digital PLL operation is subject to some change. AC timing t PWTX TX-CLK t STX TX-DATA RX-CLK RX-DATA SM8211M = unless otherwise noted Condition t PWTX t CYTX t STX t HTX t CYXT PWBR 512 bps ...

Page 5

... SM8211M 1st batch SC Sync code word 1 frame (= 2 code words) Frame number code word (32 bits) Figure 1. Receive signal format even-parity bit, making a 32-bit signal. The sync code word pattern is shown in table 1. Bit value ...

Page 6

... MSB 21-bit binary conversion Call sign 1 Bits (18 bits) Flag address signal 1 = message signal Figure 2. Call number to call sign conversion SM8211M Bit number 20, 21 Function bits 20 21 Function bits are the user-defi ...

Page 7

... SM8211M Battery Saving (BS1, BS2, BS3) The SM8211M controls the intermittent-duty opera- tion of the RF stage, which reduces battery consump- tion, and outputs three control signals (BS1, BS2, BS3). The function each signal controls in each mode is described below. BS1 (RF-control main output signal)— ...

Page 8

... Operating Modes The SM8211M has four operating modes—Switch- ON, Preamble, Idle and Lock modes. Note that all values in parentheses in the following figures are for the case when the speed is 1200 bps. Switch-ON mode After power is applied and after RST has gone LOW to reset all internal circuits, code words for the 27-bit fl ...

Page 9

... BS2 (BS2 flag = 1) BS3 Preamble signal Preamble count starts SM8211M Idle mode In idle mode, a check is made for the presence of a preamble signal when the RF intermittent-duty con- trol signals (BS1, BS2, BS3) for battery saving are active preamble pattern is detected, operation immediately transfers to preamble mode ...

Page 10

... C D Idle mode E Figure 6. Operating mode transition diagram SM8211M When one of the 24 addresses does match, ADD- DET goes HIGH for the duration of the next code word period and the corresponding 5-bit address information is transmitted to the CPU on RX-DATA in sync with RX-CLK. When the address informa- tion is confi ...

Page 11

... SM8211M Figure 7. Lock mode timing (frame ID number 3) NIPPON PRECISION CIRCUITS—11 ...

Page 12

... Address/Flag Data Transmission (CPU to SM8211M) After device reset initialization, the address and flag data is transmitted from the CPU on TX-DATA in 225 cycles in sync with the falling edge of TX-CLK. (See the description in “Switch-ON mode”). The SM8211M supports six independent addresses (identifi and F). Using these possible to cover all kinds of group calls ...

Page 13

... Table 8. Input polarity flag INV 0 1 SM8211M Receive mode set ON/OFF. ON when 1. One of eight operating conditions select (with LBO when 512/1200 bps speed select. 512 bps when 1. Frame number select Signal input (SIG-IN) normal/inverse select. Normal when 0. BS2 output signal mode select ...

Page 14

... Table 12. Digital filter constant set flags FL2 FL1 FL0 0 Digital filter not used don’t care SM8211M Table 13. Rate error detection set flags Frame number ER2 ...

Page 15

... Received Data Transmission (SM8211M to CPU) In lock mode, if the receive data for the frame is rec- ognized as one of the 24 addresses with 2 bit errors or less, then ADD-DET goes HIGH for the duration Detected address codeword Internal bit clock RX-CLK RX-DATA ADD-DET Table 14. Address set fl ...

Page 16

... If an address is detected in the second code word in the frame, ADD-DET stays HIGH for the duration of two code word periods. SM8211M ognized as a message, data reception continues and the corrected message data and error check flags are sent to the CPU. If the MSB is 0, the data is recog- nized as an address signal or idle code and data reception or data transmission to the CPU is halted ...

Page 17

... For internal oscillator operation, RST goes LOW for longer immediately after power is applied or just after a BACKUP release. After RST returns SM8211M This function is useful for checking the RF stage cir- cuits. After RST goes HIGH, the device waits for the ID code input. ...

Page 18

... Figure 12. TX-DATA load timing System Clock The SM8211M operates using a 76.8 or 153.6 kHz system clock. The clock can be set up using a crystal oscillator or an externally input clock. For crystal oscillator clocks, only a crystal needs to be connected between XT and XTN. The oscillator amplifi ...

Page 19

... Yes ID code and flags set BS3 = HIGH BS1 = BS2 = HIGH (BS1 = HIGH) BS2 = LOW (BS2 = HIGH) Preamble Parentheses indicate operation with flag BS2 = 1. SM8211M Preamble Bit clock counter reset ( Bit clock count increment ( Yes Preamble pattern No Yes Sync code detected ...

Page 20

... ADD-DET = HIGH address information transmit Yes Sync code timing No C Yes Frame timing No Address Message/Address Message Message transmit SM8211M BS2 = LOW BS1 = BS3 = LOW Message Message/Address Address No Valid address Yes Message receive flag = 0 Sync code timing Frame timing < frame Frame timing = frame ...

Page 21

... E No Sync code detected Yes SYN-VAL = HIGH SYN-VAL = HIGH SYN-VAL = LOW 1 Message receive flag 0 A SM8211M BREAK input Message receive flag = 0 and message halts within 2 bits of time Yes Frame timing B = frame No Wait until next code word D No Yes Preamble present No 1 Message receive flag ...

Page 22

... Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. SM8211M Paging Receiver System RF stage Decoder Waveform SM8211M generator decoder IC CPU D/D converter LCD driver LCD Supply Display NIPPON PRECISION CIRCUITS INC ...

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