hy5du561622dtp Hynix Semiconductor, hy5du561622dtp Datasheet
hy5du561622dtp
Available stocks
Related parts for hy5du561622dtp
hy5du561622dtp Summary of contents
Page 1
... DDR SDRAM HY5DU56422D(L)TP HY5DU56822D(L)TP HY5DU561622D(L)TP This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 /Apr. 2006 HY5DU56422D(L)TP HY5DU56822D(L)TP HY5DU561622D(L)TP 1 ...
Page 2
Revision History Revision No. First Version Release - Merged HY5DU564(8,16)22D(L)TP and 1.0 HY5DU564(8,16)22D(L)TP-D into HY5DU564(8,16)22D(L)TP. 1.1 State Diagram modified Rev. 1.1 /Apr. 2006 History HY5DU56822D(L)TP HY5DU561622D(L)TP Draft Date Remark Feb. 2005 Apr. 2006 2 ...
Page 3
DESCRIPTION The HY5DU56422D(L)TP, HY5DU56822D(L)TP and HY5DU561622D(L)TP are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced ...
Page 4
PIN CONFIGURATION x4 x8 VDD VDD NC DQ0 VDDQ VDDQ NC NC DQ0 DQ1 VSSQ VSSQ DQ2 VDDQ VDDQ NC NC DQ1 DQ3 VSSQ VSSQ VDDQ VDDQ VDD VDD ...
Page 5
PIN DESCRIPTION PIN TYPE CK, /CK Input CKE Input /CS Input BA0, BA1 Input A0 ~ A12 Input /RAS, /CAS, /WE Input DM Input (LDM,UDM) DQS I/O (LDQS,UDQS Supply Supply DDQ SSQ ...
Page 6
FUNCTIONAL BLOCK DIAGRAM (64Mx4) 4Banks x 16Mbit x 4 I/O Double Data Rate Synchronous DRAM CLK /CLK CKE Command /CS Decoder /RAS /CAS /WE ADD Address Buffer BA Rev. 1.1 /Apr. 2006 Write Data Register 2-bit Prefetch Unit 8 Bank ...
Page 7
FUNCTIONAL BLOCK DIAGRAM (32Mx8) 4Banks x 8Mbit x 8 I/O Double Data Rate Synchronous DRAM CLK /CLK CKE Command /CS Decoder /RAS /CAS /WE ADD Address Buffer BA Rev. 1.1 /Apr. 2006 Write Data Register 2-bit Prefetch Unit 16 Bank ...
Page 8
FUNCTIONAL BLOCK DIAGRAM (16Mx16) 4Banks x 4Mbit x 16 I/O Double Data Rate Synchronous DRAM CLK /CLK CKE Command /CS Decoder /RAS /CAS /WE ADD Address Buffer BA Rev. 1.1 /Apr. 2006 Write Data Register 2-bit Prefetch Unit 32 Bank ...
Page 9
SIMPLIFIED COMMAND TRUTH TABLE Command CKEn-1 1,2 Extended Mode Register Set 1,2 Mode Register Set 1 Device Deselect 1 No Operation 1 Bank Active 1 Read 1,3 Read with Autoprecharge 1 Write 1,4 Write with Autoprecharge 1,5 Precharge All Banks ...
Page 10
WRITE MASK TRUTH TABLE Function CKEn-1 1 Data Write 1 Data-In Mask Note: 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 data I/O, ...
Page 11
SIMPLIFIED STATE DIAGRAM lie ...
Page 12
POWER-UP SEQUENCE AND DEVICE INITIALIZATION DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally ...
Page 13
Power-Up Sequence VDD VDDQ tVTD VTT VREF /CLK CLK tIS tIH LVCMOS Low Level CKE CMD NOP DM ADDR A10 BA0, BA1 DQS DQ'S T=200usec Power UP VDD and CK stable Rev. 1.1 /Apr. 2006 PRE EMRS MRS NOP PRE ...
Page 14
MODE REGISTER SET (MRS) The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is ...
Page 15
BURST DEFINITION Burst Length Starting Address (A2,A1,A0 BURST LENGTH & TYPE Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column ...
Page 16
CAS LATENCY The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks ...
Page 17
EXTENDED MODE REGISTER SET (EMRS) The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func- tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The Extended ...
Page 18
ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature (Ambient) Storage Temperature Voltage on V relative Voltage on V relative to V DDQ SS Voltage on inputs relative Voltage on I/O pins relative ...
Page 19
IDD SPECIFICATION AND CONDITIONS Test Conditions Operating Current: One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: One bank; Active - Read ...
Page 20
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7 IDD1: Operating current: One bank operation 1. Typical Case: VDD = 2.5V, T=25 2. Worst Case: VDD = 2.7V Only one bank is accessed with tRC(min), Burst Mode, ...
Page 21
IDD Specification 64Mx4 Parameter Operating Current Operating Current Precharge Power Down Standby Current Idle Standby Current Idle Quiet Standby Current Active Power Down Standby Current Active Standby Current Operating Current Operating Current Auto Refresh Current Normal Self Refresh Current Low ...
Page 22
Parameter Operating Current Operating Current Precharge Power Down Standby Current Idle Standby Current Idle Quiet Standby Current Active Power Down Standby Current Active Standby Current Operating Current Operating Current Auto Refresh Current Normal Self Refresh Current Low Power Operating ...
Page 23
AC OPERATING CONDITIONS Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Note: ...
Page 24
AC CHARACTERISTICS Parameter Symbol Row Cycle Time tRC Auto Refresh Row tRFC Cycle Time Row Active Time tRAS Active to Read with tRCD or tRAP tRASmin Auto Precharge Delay Row Address to tRCD Column Address Delay Row Active to Row ...
Page 25
Parameter Symbol Data-out high-impedance window 10 from CK,/CK Data-out low-impedance window 10 from CK, /CK Input Setup Time (fast slew 14,16-18 rate) Input Hold Time (fast slew 14,16-18 rate) Input Setup Time (slow slew 15-18 rate) Input Hold Time (slow ...
Page 26
Note: 1. All voltages referenced to Vss. 2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage ...
Page 27
The pulse duration distortion of on-chip clock circuits; and ...
Page 28
SYSTEM CHARACTERISTICS CONDITIONS for DDR SDRAMS The following tables are described specification parameters that required in systems using DDR devices to ensure proper performannce. These characteristics are for system simulation purposes and are guaranteed by design. Input Slew Rate for ...
Page 29
Note: 1. Pullup slew rate is characterized under the test conditions as shown in below Figure. Output (VOUT) 50 VSSQ 2. Pulldown slew rate is measured under the test conditions shown in below Figure. VDDQ Output (VOUT) 3. Pullup slew ...
Page 30
CAPACITANCE o (T =25 C, f=100MHz) A Parameter Input Clock Capacitance Delta Input Clock Capacitance Input Capacitance Delta Input Capacitance Input / Output Capacitance Delta Input / Output Capacitance Note: 1. VDD = min. to max., VDDQ = 2.3V to ...
Page 31
PACKAGE INFORMATION 400mil 66pin Thin Small Outline Package 0.65 (0.0256) BSC 1.194 (0.0470) 0.991 (0.0390) Rev. 1.1 /Apr. 2006 BASE PLANE 22.33 (0.879) 22.12 (0.871) 0.35 (0.0138) 0.25 (0.0098) SEATING PLANE HY5DU56822D(L)TP HY5DU561622D(L)TP max , Unit : mm(Inch) min 11.94 ...