sza1000 NXP Semiconductors, sza1000 Datasheet
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sza1000 Summary of contents
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... DATA SHEET SZA1000 QIC digital equalizer Product specification File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 1998 Feb 16 ...
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... Mbits/s for floppy tape drives and Mbits/s for drives with internal controllers. GENERAL DESCRIPTION The SZA1000 is a single chip digital equalizer for single channel QIC (Quarter Inch Cartridge) systems with MR (Magneto Resistive) heads. It can be used with QIC 3010, QIC 3020, QIC 3080, QIC 3095, Travan and 5, and similar formats ...
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... Acrobat reader. white to force landscape pages to be ... 37 V ref 32 INA ADC HPF 33 INB 30 RESET SZA1000 31 TEST AUXBUS0/WDOUT AUXBUS1 I/O to MUX 8 AUXBUS7 10 WDIN 4 WGATE WRITE 9 EQUALIZATION WEQCLK 3 WEQEN 36 WGX ...
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... LOW positive A/D reference voltage input connect external resistor differentiated signal; positive output comparator for read pulse; positive input 4 Product specification SZA1000 ...
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... Feb 16 analog ground analog supply voltage comparator for read pulse; negative input differentiated signal; negative output SZA1000 Fig.2 Pin configuration. 5 Product specification SZA1000 DESCRIPTION 33 INB 32 INA 31 TEST 30 RESET 29 PACLK 28 V SSD2 27 SRD/ DDD2 25 RRC ...
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... Philips Semiconductors QIC digital equalizer FUNCTIONAL DESCRIPTION Clock oscillator and divider The clock source for the SZA1000 can be a crystal connected between pins 6 and external clock signal connected to pin 6. This clock frequency is divided by a number programmable between 1 and 8 (see Tables 27 and 28). The resulting frequency, f used as clock input to all on-chip circuits except the write equalizer ...
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... Uncommitted current sources MGG583 Two uncommitted 5-bit programmable current sink DACs ( mA) are available as IO1 and IO2 (see Table 20 for programming). These could be used, for example, to drive the tape hole detector circuit. 7 Product specification SZA1000 MGG584 Fig.4 SRD/RRC timing ...
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... PLL frequency can be read via the serial interface. To read data from the status registers, hex address FF must be transmitted along with the required data code. The IC will then respond with the contents of the appropriate 8-bit status register (see Table 44). 8 Product specification SZA1000 ...
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Acrobat reader. white to force landscape pages to be ... SDEN SCLK SDIO SDEN SCLK SDIO A7 A6 ...
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... Amplitude detector slope qualification delay (see Table 10) Gap detector fixed threshold WEQ settings (see Tables 13 and 14) WEQ settings (see Tables 15, 16 and 17) WEQ clock divider (see Tables 18 and 19) not used IO1 DAC current (see Table 20) IO2 DAC current (see Table 20) 10 Product specification SZA1000 ...
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... PLL loop filter integrating gain and range PLL loop filter proportional gain maximum likelihood detector settings FIR_VALn.4 FIR_VALn.3 TAPS FS0.2 FS1.2 FS2.2 FS3.2 FS4 Product specification SZA1000 DESCRIPTION D2 D1 FIR_VALn.2 FIR_VALn.1 FIR_VALn FS0.1 FS0.0 FS5.2 FS5.1 FS1.1 FS1.0 FS6.2 FS6.1 FS2.1 FS2 ...
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... See Table 7 for the values of LPF_VALn.n 1998 Feb 16 TAP 1,6 TAP 2 FIR OUTPUT SCALING GAIN FACTOR Product specification SZA1000 TAP 3,8 TAP 4,9 TAP ...
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... LPF_VAL2 LPF_VAL1 +128 +128 LPF_VAL1 LPF_VAL2 LPF_VAL3 LPF OUTPUT SCALING GAIN FACTOR GP.2 GP.1 GP.0 13 Product specification SZA1000 COEFFICIENT VALUES LPF_VAL6 LPF_VAL5 LPF_VAL4 LPF_VAL3 LPF_VAL2 LPF_VAL1 +128 +128 LPF_VAL1 LPF_VAL2 LPF_VAL3 LPF_VAL4 LPF_VAL5 LPF_VAL6 ...
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... Table 12 Variable qualifier threshold s 500 --------- - f s 1000 ------------ - f s 2000 ------------ - f s 4000 ------------ - Product specification SZA1000 D2 D1 DEL.0 SL.1 GP, GN VARIABLE THRESHOLD ...
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... T 1 etc Fig.7 Position and width of write equalization pulse. 1998 Feb TPS2 TPS1 Fig.6 WD/WDI signal timing Product specification SZA1000 D2 D1 TPS0 TWS1 MGG586 MGG587 D0 TWS0 ...
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... Table 17 Write equalization pulse width IDn.4 IDn.3 IDn --------- - mA Product specification SZA1000 TWS WIDTH IN TIME SLOTS 0 WEQ off WCD.2 WCD IDn.2 IDn.1 D0 WCD.0 D0 IDn.0 ...
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... DL2.1 Table 26 Differentiator gain factor CYCLES Product specification SZA1000 PA.0 GAP.1 GAP.0 OUTPUT SIGNAL ON PIN PACLK PACLK off 0 - PACLK off 0 - PACLK off DL2.0 DL1.1 DL1.0 OUTPUT SCALING GAIN FACTOR ...
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... R1 selects the filter sample rate reduction factor; STBY1 and STBY2 are the DAC and ADC power on/off switches; ST selects output signal modes for pins 25 and 27. 1998 Feb SF.4 SF FUNCTIONS ST.3 ST.2 ST.1 18 Product specification SZA1000 CD.2 CD.1 CD SF.2 SF.1 SF ST.0 STBY1 R1 ...
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... D4 D3 PF.5 PF.4 PF ------------ - s 2048 19 Product specification SZA1000 Table 33 ADC power STBY2 A/D POWER 0 1 AUXBUS (1) bit 0: WDOUT, bits high-Z (2) bit 0: WDOUT, bits high-Z bit 0: WDOUT, bits high-Z ADC output DAC output 8-bit input to HPF 8-bit input to HPF ...
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... Feb RNG.0 NI2 Table 40 PLL range 128 1 256 1 512 NP2.1 NP2.0 20 Product specification SZA1000 WIN_SHIFT degrees NI2.0 NI1 RNG PLL RANGE 128 2 256 3 512 D2 D1 NP1.2 NP1 NI1.0 D0 ...
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... Feb (3) (4) (5) PR0 ks3 positive peaks in measured level negative peaks in measured level measured peak-to-peak level low-pass filtered LEVEL_ABS FREQ f ----------------- - s 256 21 Product specification SZA1000 (5) (5) ks2 ks1 DESCRIPTION actual frequency of PLL ...
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... In accordance with “SNW-FQ-611-E” . 1998 Feb 16 CONDITIONS MIN. 0.3 0.3 0.3 0.3 0 note 1 3000 note 2 300 series resistance and a 2.5 H series inductance. CONDITIONS VALUE in free air 70 22 Product specification SZA1000 MAX. UNIT +5.5 V +5.5 V +5 +50 mA +10 mA +1100 mW +85 C +125 C +150 ...
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... STBY 1= 1; STBY2 = 0 see Table 14; (3080; 3095) 0. I/O pins high-Z; note 1 1.8 1.0 2 2.3 ) ref see Table 20 IDAC1 = 31 1.40 see Table 20 IDAC2 = 31 1.40 note 2 1.5 note 2 1.0 23 Product specification SZA1000 = unless otherwise ref MIN. TYP. MAX. 5.0 5.5 5.0 5.5 5.0 5.5 5.0 5 0.3V DD 0.5 0.5 5 2.0 2.2 1.7 2.1 1.6 2 ...
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... CLKINH 0.2C o(L)(RRC) note CLKINL 0.2C o(L)(RRC) note CLKINH 0.2C o(L)(PACLK) note CLKINL 0.2C o(L)(PACLK) note 8 notes 7 and 8 24 Product specification SZA1000 TYP. MAX. UNIT 8 MHz 1.16 1 MHz ...
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... see Table 14 WDI_I = 0; 10 see Table 15 note 0.2 WEQH C o(L)(WDOUT 0.5 see Table 14 < 50 pF. o(L)(SRD) < 50 pF. o(L)(RRC) < 50 pF. o(L)(PACLK) o(L)(AUX) < 50 pF. o(L)(WDOUT) 25 Product specification SZA1000 TYP. MAX. UNIT 36 MHz 24 24 MHz WEQH % < 50 pF. ...
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Acrobat reader. white to force landscape pages to be ... Serial interface t su(EN-CLK) t h(EN-CLK) t su(D-CLK) t h(D-CLK) SDEN SCLK SDIO A7 ...
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... WEQCLK) WDIN (WDI mode) WDIN (WD mode) WDOUT (WDI mode) Fig.10 WEQ section showing set-up and hold timing. 1998 Feb 16 t h(SRD-RRC) t su(AUX-CLKIN) t CLKINH t d(PACLK-AUX) t PACLKH t WEQH t WEQL t h(WD-WEQCLK) t IL(WDIN) t OL(WDOUT) 27 Product specification SZA1000 t h(AUX-CLKIN) t d(AUX-PACLK) MGG657 t su(WD-WEQCLK) MGG658 ...
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... 2 scale (1) ( 0.25 10.1 10.1 12.9 12.9 0.8 1.3 0.14 9.9 9.9 12.3 12.3 REFERENCES JEDEC EIAJ 28 Product specification SZA1000 SOT307 detail X (1) ( 0.95 1.2 1.2 10 0.15 0.15 0.1 o 0.55 0.8 0.8 0 EUROPEAN ISSUE DATE PROJECTION 95-02-04 97-08-01 ...
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... Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 29 Product specification SZA1000 ...
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... Philips customers using or selling these products for use in such applications their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Feb 16 30 Product specification SZA1000 ...
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... Philips Semiconductors QIC digital equalizer 1998 Feb 16 NOTES 31 Product specification SZA1000 ...
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Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, ...