ST10F272B_12 STMICROELECTRONICS [STMicroelectronics], ST10F272B_12 Datasheet

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ST10F272B_12

Manufacturer Part Number
ST10F272B_12
Description
16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
Features
June 2012
This is information on a product in full production.
16-bit CPU with DSP functions
– 31.25ns instruction cycle time at 64MHz
– Multiply/accumulate unit (MAC) 16 x 16-bit
– Enhanced boolean bit manipulations
– Single-cycle context switching support
On-chip memories
– 256 Kbyte Flash memory (32-bit fetch)
– Single voltage Flash memories with
– Up to 16 Mbyte linear address space for
– 2 Kbyte internal RAM (IRAM)
– 10/18 Kbyte extension RAM (XRAM)
– Programmable external bus configuration &
– Five programmable chip-select signals
– Hold-acknowledge bus arbitration support
Interrupt
– 8-channel peripheral event controller for
– 16-priority-level interrupt system with 56
Timers
– Two multi-functional general purpose timer
Two 16-channel capture / compare units
4-channel PWM unit + 4-channel XPWM
16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM
max CPU clock
multiplication, 40-bit accumulator
erase/program controller and 100K
erasing/programming cycles.
code and data (5 Mbytes with CAN or I
characteristics for different address ranges
single cycle interrupt driven data transfer
sources, sampling rate down to 15.6ns
units with 5 timers
Doc ID 11917 Rev 3
2
C)
A/D converter
– 24-channel 10-bit
– 3 μs minimum conversion time
Serial channels
– Two synch. / asynch. serial channels
– Two high-speed synchronous channels
– One I
2 CAN 2.0B interfaces operating on 1 or 2 CAN
busses (64 or 2x32 message, C-CAN version)
Fail-safe protection
– Programmable watchdog timer
– Oscillator watchdog
On-chip bootstrap loader
Clock generation
– On-chip PLL with 4 to 8 MHz oscillator
– Direct or prescaled clock input
Real time clock and 32 kHz on-chip oscillator
Up to 111 general purpose I/O lines
– Individually programmable as input, output
– Programmable threshold (hysteresis)
Idle, power down and stand-by modes
Single voltage supply: 5V ±10%
PQFP144 (28 x 28 x 3.4mm)
(Plastic Quad Flat Package)
or special function
2
C standard interface
Datasheet
ST10F272B
ST10F272E
LQFP144 (20 x 20 x 1.4mm)
(Thin Quad Flat Package)
production data
www.st.com
1/188
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ST10F272B_12 Summary of contents

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MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM Features ■ 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit (MAC 16-bit multiplication, 40-bit accumulator – Enhanced ...

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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST10F272B/ST10F272E 5.5.5 5.5.6 5.5.7 5.5.8 5.5.9 5.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST10F272B/ST10F272E 21.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 24.8.6 24.8.7 24.8.8 24.8.9 24.8.10 PLL lock / unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST10F272B/ST10F272E List of tables Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables Table 49. Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST10F272B/ST10F272E List of figures Figure 1. Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures Figure 49. External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE 166 Figure 50. External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE. . 167 Figure 51. External memory cycle: Multiplexed bus, ...

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ST10F272B/ST10F272E 1 Introduction 1.1 Description The ST10F272B / E device is a STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. The ST10F272B / E combines high CPU performance ( million instructions per second) with high peripheral functionality and ...

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Introduction for the RAM, the low-voltage section of the 32kHz oscillator and the Real Time Clock module when not disabled allowed to exceed the upper limit for a very short period of time during the ...

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ST10F272B/ST10F272E Clock module, the Power-down consumption is dominated by the consumption of the oscillator amplifier itself. A second on-chip oscillator amplifier circuit (32kHz) is implemented for low power modes: it can be used to provide the reference to the Real ...

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Introduction Figure 1. Logic symbol 14/188 Doc ID 11917 Rev 3 ST10F272B/ST10F272E ...

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ST10F272B/ST10F272E 2 Pin data Figure 2. Pin configuration (top view) P6.0 / CS0 P6.1 / CS1 P6.2 / CS2 P6.3 / CS3 P6.4 / CS4 P6.5 / HOLD / SCLK1 P6.6 / HLDA / MTSR1 P6.7 / BREQ / MRST1 ...

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Pin data Table 1. Pin description Symbol Pin Type I ... ... 5 O P6 I/O 9-16 I/O I ... ... I/O 12 ...

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ST10F272B/ST10F272E Table 1. Pin description (continued) Symbol Pin Type 19-26 I P7.0 - P7.7 ... ... I/O ... ... 26 I/O 27-36 I 39- P5 P5.10 - P5.15 ...

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Pin data Table 1. Pin description (continued) Symbol Pin Type 65-70, I/O 73-80, I P3 P3.6 - P3.13, P3. ...

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ST10F272B/ST10F272E Table 1. Pin description (continued) Symbol Pin Type 85-92 I P4.0 –P4 ...

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Pin data Table 1. Pin description (continued) Symbol Pin Type STBY P0L.0 -P0L.7, 100-107, P0H.0 108, I/O P0H.1 - 111-117 P0H.7 20/188 External access enable pin. A low level applied to this pin during and ...

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ST10F272B/ST10F272E Table 1. Pin description (continued) Symbol Pin Type 118-125 I/O 128-135 P1L.0 - P1L.7 P1H.0 - P1H.7 132 I 133 I 134 I 135 I XTAL1 138 I XTAL2 137 O XTAL3 143 I XTAL4 144 O RSTIN 140 ...

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Pin data Table 1. Pin description (continued) Symbol Pin Type RPD 84 - 17, 46, 72,82, 109, 126, 136 18,45, 55,71, V 83,94 110, 127, 139 22/188 Timing pin for ...

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ST10F272B/ST10F272E 3 Functional description The architecture of the ST10F272 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure ...

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Memory organization 4 Memory organization The memory space of the ST10F272 is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16M Bytes. The entire memory ...

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ST10F272B/ST10F272E external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. After reset the XRAM2 is mapped from address 09’0000h. XRAM2 represents also the Stand-by RAM, which can be maintained biased through EA / VSTBY pin when ...

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Memory organization ASC1: Address range 00’E900h - 00’E9FFh is reserved for the ASC1 Module access. The ASC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON register. Accesses to the ASC1 Module ...

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ST10F272B/ST10F272E Figure 4. ST10F272 on-chip memory mapping (ROMEN=1 / XADRS = 800Bh - Reset value) Doc ID 11917 Rev 3 Memory organization 27/188 ...

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Internal Flash memory 5 Internal Flash memory 5.1 Overview The on-chip Flash is composed by one matrix module, 256 KBytes wide. This module is on ST10 Internal bus called IFLASH Figure 5. Flash structure The programming operations ...

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ST10F272B/ST10F272E 5.2.2 Modules structure The IFLASH module is composed by a bank (Bank 0) of 256 Kbyte of Program Memory divided in 8 sectors (B0F0...B0F7). Bank 0 contains also a reserved sector named Test- Flash. The Addresses from 0x08 0000 ...

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Internal Flash memory When Bootstrap mode is entered: ● Test-Flash is seen and available for code fetches (address 00’0000h) ● User I-Flash is only available for read and write accesses ● Write accesses must be made with addresses starting in ...

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ST10F272B/ST10F272E 5.3 Write operation The Flash module have one single register interface mapped in the memory space of the IBUS (0x08 0000 to 0x08 0015). All the operations are enabled through four 16-bit control registers: Flash Control Register 1-0 High/Low ...

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Internal Flash memory 5.4 Registers description 5.4.1 Flash control register 0 low The Flash Control Register 0 Low (FCR0L) together with the Flash Control Register 0 High (FCR0H) is used to enable and to monitor all the write operations on ...

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ST10F272B/ST10F272E 5.4.2 Flash control register 0 high The Flash Control Register 0 High (FCR0H) together with the Flash Control Register 0 Low (FCR0L) is used to enable and to monitor all the write operations on the IFLASH. The user has ...

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Internal Flash memory Table 8. Flash control register 0 high (continued) Bit Suspend This bit must be set to suspend the current Program (Word or Double Word) or Sector Erase operation in order to read data in one of the ...

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ST10F272B/ST10F272E 5.4.4 Flash control register 1 high The Flash Control Register 1 High (FCR1H), together with Flash Control Register 1 Low (FCR1L), is used to select the Sectors to Erase, or during any write operation to monitor the status of ...

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Internal Flash memory Table 12. Flash data register 0 low Bit Data Input 15:0 These bits must be written with the Data to program the Flash with the following DIN(15:0) operations: Word Program (32-bit), Double Word Program (64-bit) and Set ...

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ST10F272B/ST10F272E Table 15. Flash data register 1 high Bit Data Input 31:16 These bits must be written with the Data to program the Flash with the following DIN(31:16) operations: Word Program (32-bit), Double Word Program (64-bit) and Set Protection. 5.4.9 ...

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Internal Flash memory 5.4.11 Flash error register Flash Error register, as well as all the other Flash registers, can be properly read only once LOCK bit of register FCR0L is low. Nevertheless, its content is updated when also BSY0 bit ...

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ST10F272B/ST10F272E 5.5 Protection strategy The protection bits are stored in Non Volatile Flash cells inside IFLASH module, that are read once at reset and stored in 4 Volatile registers. Before they are read from the Non Volatile cells, all the ...

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Internal Flash memory 5.5.3 Flash non volatile access protection register 0 FNVAPR0 (0x08 DFB8 Table 20. Flash non volatile access protection register 0 Bit Access Protection This bit, if programmed at 0, disables any access (read/write) to ...

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ST10F272B/ST10F272E 5.5.5 Flash non volatile access protection register 1 high FNVAPR1H (0x08 DFBE PEN15PEN14PEN13PEN12PEN11PEN10 PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0 Table 22. Flash non volatile access protection register 1 high ...

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Internal Flash memory way can be executed a maximum of 16 times. To execute the above described operations, the Flash has to be temporary unprotected (See Trying to write into the access protected Flash from internal RAM or external memories ...

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ST10F272B/ST10F272E To temporary unprotect the Flash when the Access Protection is active necessary to set at 1 the bit TAUB in XFVTAUR0. This bit can be write at 1, only executing from Flash: in this way only an ...

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Internal Flash memory 5.6 Write operation examples In the following, examples for each kind of Flash write operation are presented. Note: The write operation commands must be executed from another memory (internal RAM or external memory ST10F269 device. ...

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ST10F272B/ST10F272E Suspend and resume Word Program, Double Word Program, and Sector Erase operations can be suspended in the following way: FCR0H |= 0x4000; Then the operation can be resumed in the following way: FCR0H |= 0x0800; FCR0H |= 0x8000; Before ...

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Internal Flash memory A Sector Erase can be suspended by setting SUSP bit. ● To perform a Word Program operation during Erase Suspend, firstly bits SUSP and SER must be reset, then bit WPG and WMS can be set. ● ...

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ST10F272B/ST10F272E 5.7 Write operation summary In general, each write operation is started through a sequence of 3 steps: 1. The first instruction is used to select the desired operation by setting its corresponding selection bit in the Flash Control Register ...

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Bootstrap loader 6 Bootstrap loader ST10F272 implements Boot capabilities in order to: ● Support bootstrap via UART or bootstrap via CAN for the standard bootstrap. ● Support a Selective Bootstrap Loader, to manage the bootstrap sequence in a different way. ...

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ST10F272B/ST10F272E 6.3 Alternate and selective boot mode (ABM and SBM) 6.3.1 Activation of the ABM and SBM Alternate boot is activated with the combination ‘01’ on Port0L[5..4] at the rising edge of RSTIN. 6.3.2 User mode signature integrity check The ...

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Central processing unit (CPU) 7 Central processing unit (CPU) The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask ...

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ST10F272B/ST10F272E 7.1 Multiplier-accumulator unit (MAC) The MAC co-processor is a specialized co-processor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms. The standard ST10 CPU has been modified to ...

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Central processing unit (CPU) 7.2 Instruction set summary The Table 27 lists the instructions of the ST10F272. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Table 27. Standard instruction set summary Mnemonic ADD(B) ...

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ST10F272B/ST10F272E Table 27. Standard instruction set summary (continued) Mnemonic J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Description Jump relative if ...

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Central processing unit (CPU) 7.3 MAC co-processor specific instructions The Table 28 lists the MAC instructions of the ST10F272. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Note that all MAC instructions are ...

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ST10F272B/ST10F272E 8 External bus controller All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required one of four different ...

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Interrupt system 9 Interrupt system The interrupt response time for internal program execution is from 78ns to 187.5ns at 64 MHz CPU clock. The ST10F272 architecture supports several mechanisms for fast and flexible response to service requests that can be ...

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ST10F272B/ST10F272E Table 29. Interrupt sources (continued) Source of Interrupt or PEC Service Request CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 ...

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Interrupt system Table 29. Interrupt sources (continued) Source of Interrupt or PEC Service Request GPT2 Timer 6 GPT2 CAPREL Register A/D Conversion Complete A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC ...

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ST10F272B/ST10F272E When different sources submit an interrupt request, the enable bits (Byte High of XIRxSEL register) define a mask which controls which sources will be associated with the unique available vector. If more than one source is enabled to issue ...

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Interrupt system Table 30. X-Interrupt detailed mapping (continued) ASC1 Transmit ASC1 Transmit Buffer ASC1 Error PLL Unlock / OWD PWM1 Channel 3...0 9.2 Exception and error traps list Table 31 shows all of the possible exceptions or error conditions that ...

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ST10F272B/ST10F272E 10 Capture / compare (CAPCOM) units The ST10F272 has two 16-channel CAPCOM units which support generation and control of timing sequences channels with a maximum resolution of 125ns at 64 MHz CPU clock. The CAPCOM ...

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Capture / compare (CAPCOM) units Table 32. Compare modes Compare modes Interrupt-only compare mode; several compare interrupts per timer period are Mode 0 possible Pin toggles on each compare match; several compare events per timer period are Mode 1 possible ...

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ST10F272B/ST10F272E 11 General purpose timer unit The GPT unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The ...

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General purpose timer unit Table 35. GPT1 timer input frequencies, resolutions and periods at 40 MHz MHz CPU Resolution Period 13.1ms maximum Table 36. GPT1 timer input frequencies, resolutions and periods at 64 MHz ...

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ST10F272B/ST10F272E 11.2 GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock ...

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General purpose timer unit Figure 10. Block diagram of GPT2 66/188 Doc ID 11917 Rev 3 ST10F272B/ST10F272E ...

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ST10F272B/ST10F272E 12 PWM modules Two pulse width modulation modules are available on ST10F272: standard PWM0 and XBUS PWM1. They can generate up to four PWM output signals each, using edge-aligned or centre-aligned PWM. In addition, the PWM modules can generate ...

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PWM modules Table 40. PWM unit frequencies and resolutions at 64 MHz CPU clock Mode 0 Resolution CPU Clock/1 15.6ns CPU Clock/64 Mode 1 Resolution CPU Clock/1 15.6ns CPU Clock/64 68/188 8-bit 10-bit 250 kHz 62.5 kHz 1.0μs 3.91 kHz ...

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ST10F272B/ST10F272E 13 Parallel ports 13.1 Introduction The ST10F272 MCU provides up to 111 I/O lines with programmable features. These capabilities bring very flexible adaptation of this MCU to wide range of applications. ST10F272 has nine groups of I/O lines gathered ...

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Parallel ports 13.2.2 Input threshold control The standard inputs of the ST10F272 determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be selected instead of the standard ...

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ST10F272B/ST10F272E This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. There are port lines, however, where the direction of the port line is switched automatically. For instance, in the ...

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A/D converter 14 A/D converter A 10-bit A/D converter with 16+8 multiplexed input channels and a sample and hold circuit is integrated on-chip. An automatic self-calibration adjusts the A/D converter module to process parameter variations at each reset event. The ...

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ST10F272B/ST10F272E register. The data can be transferred to the RAM by interrupt software management or using the PEC data transfer. ● Wait for ADDAT read mode: When using continuous modes, in order to avoid to overwrite the result of the ...

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Serial channels 15 Serial channels Serial communication with other microcontrollers, microprocessors, terminals or external peripheral components is provided four serial interfaces: two asynchronous / synchronous serial channels (ASC0 and ASC1) and two high-speed synchronous serial channel (SSC0 ...

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ST10F272B/ST10F272E Table 42. ASC asynchronous baud rates by reload value and deviation errors (f S0BRS = ‘0’, f CPU Baud rate (baud) Deviation error 2 000 000 0.0% / 0.0% 112 000 +1.5% / -7.0% 56 000 +1.5% / -3.0% ...

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Serial channels Table 43. ASC synchronous baud rates by reload value and deviation errors (f S0BRS = ‘0’, f CPU Baud rate (baud) Deviation error 900 0.0% / 0.0% 612 0.0% / 0.0% Table 44. ASC synchronous baud rates by ...

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ST10F272B/ST10F272E Table 45 and Table 46 the resulting bit times for 40 MHz and 64 MHz CPU clock respectively. The maximum is anyway limited to 8Mbaud. Table 45. Synchronous baud rate and reload values (f Baud rate Reserved Can be ...

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I2C interface 16 I2C interface 2 The integrated I C Bus Module handles the transmission and reception of frames over the two-line SDA/SCL in accordance with the I operate in slave mode, in master mode or in multi-master mode. It ...

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ST10F272B/ST10F272E 17 CAN modules The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active based on the C-CAN ...

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CAN modules Single CAN bus The single CAN Bus multiple interfaces configuration may be implemented using two CAN transceivers as shown in Figure 12. Connection to single CAN bus via separate CAN transceivers The ST10F272 also supports single CAN Bus ...

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ST10F272B/ST10F272E Multiple CAN bus The ST10F272 provides two CAN interfaces to support such kind of bus configuration as shown in Figure 14. Figure 14. Connection to two different CAN buses (e.g. for gateway application) Parallel Mode In addition to previous ...

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Real time clock 18 Real time clock The Real Time Clock is an independent timer, in which the clock is derived directly from the clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator) so that ...

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ST10F272B/ST10F272E 19 Watchdog timer The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in ...

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System reset 20 System reset System reset initializes the MCU in a predefined state. There are six ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 49. Reset event definition ...

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ST10F272B/ST10F272E 20.2 Asynchronous reset An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low level. Then the ST10F272 is immediately (after the input filter delay) forced in reset default state. It pulls low ...

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System reset Warning: In Figure 16 and respectively with boot from internal or external memory, highlighting the reset phase extension introduced by the embedded FLASH module when selected. Note: Never power the device without keeping RSTIN pin grounded: the device ...

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ST10F272B/ST10F272E Figure 16. Asynchronous power-on RESET ( Doc ID 11917 Rev 3 System reset 87/188 ...

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System reset Figure 17. Asynchronous power-on RESET ( TLC depending on clock source selection. Hardware reset The asynchronous reset must be used to recover from catastrophic situations of the application. It may be triggered ...

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ST10F272B/ST10F272E Figure 18. Asynchronous hardware RESET ( Longer than Port0 settling time + PLL synchronization (if needed, that is P0 (15:13) changed). 1. Longer than 500ns to take into account of Input Filter on RSTIN pin. 2. Doc ...

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System reset Figure 19. Asynchronous hardware RESET ( Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed) Longer than 500ns to take into account of Input Filter on RSTIN pin 3 to ...

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ST10F272B/ST10F272E Short and long synchronous reset Once the first maximum 16 TCL are elapsed (4+12TCL), the internal reset sequence starts 1024 TCL cycles long: at the end of it, and after other 8TCL the level of RSTIN is ...

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System reset timing of a typical synchronous Long Reset, again when booting from internal or external memory. Synchronous reset and RPD pin Whenever the RSTIN pin is pulled low (by external hardware consequence of a Bidirectional reset), ...

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ST10F272B/ST10F272E Figure 20. Synchronous short / long hardware RESET ( RSTIN assertion can be released there. Refer also during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5 V ...

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System reset Figure 21. Synchronous short / long hardware RESET ( RSTIN assertion can be released there. Refer also during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5 ...

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ST10F272B/ST10F272E Figure 22. Synchronous long hardware RESET ( during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation),the asynchronous reset is then immediately entered. Even if RPD returns ...

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System reset Figure 23. Synchronous long hardware RESET ( during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. 2. Minimum ...

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ST10F272B/ST10F272E 20.5 Watchdog timer reset When the watchdog timer is not disabled during the initialization, or serviced regularly during program execution, it overflows and trigger the reset sequence. Unlike hardware and software resets, the watchdog reset completes a running external ...

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System reset Figure 25 WDT unidirectional RESET ( 20.6 Bidirectional reset As shown in the previous sections, the RSTOUT pin is driven active (low level) at the beginning of any reset sequence (synchronous/asynchronous hardware, software and ...

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ST10F272B/ST10F272E or Watchdog Reset become a Short Hardware Reset. On the contrary, if RSTF remains low for less than 4 TCL, the device simply exits reset state. The Bidirectional reset is not effective in case RPD is held low, when ...

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System reset Figure 26 WDT bidirectional RESET (EA=1) 100/188 Doc ID 11917 Rev 3 ST10F272B/ST10F272E ...

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ST10F272B/ST10F272E Figure 27 WDT bidirectional RESET ( Doc ID 11917 Rev 3 System reset 101/188 ...

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System reset Figure 28 WDT bidirectional RESET (EA=0) followed RESET 20.7 Reset circuitry Internal reset circuitry is described in resistor of 50kΩ to 250kΩ (The minimum reset time must be calculated using the lowest value). ...

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ST10F272B/ST10F272E To ensure correct power-up reset with controlled supply current consumption, specially if clock signal requires a long period of time to stabilize, an asynchronous hardware reset is required during power-up. For this reason recommended to connect the ...

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System reset Figure 30. System reset circuit Figure 31. Internal (simplified) reset circuitry 104/188 Doc ID 11917 Rev 3 ST10F272B/ST10F272E ...

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ST10F272B/ST10F272E 20.8 Reset application examples Next two timing diagrams bidirectional internal reset events (Software and Watchdog) including in particular the external capacitances charge and discharge transients (refer also to external circuit scheme). Figure 32. Example of software or watchdog bidirectional ...

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System reset Figure 33. Example of software or watchdog bidirectional reset ( 106/188 Doc ID 11917 Rev 3 ST10F272B/ST10F272E ...

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ST10F272B/ST10F272E 20.9 Reset summary A summary of the different reset events is reported in Table 50. Reset event Event Asynch. Power-on Reset Asynch Asynch. 0 ...

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System reset Table 50. Reset event (continued) Event Synch Synch. (2) Software Reset Synch Synch Synch Synch. (2) Watchdog Reset 0 1 ...

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ST10F272B/ST10F272E Figure 34. PORT0 bits latched into the different registers after reset H.7 H.6 CLKCFG RP0H CLKCFG Clock Generator P0L.7 ROMEN 10 9 PORT0 H.5 H.4 H.3 H.2 H.1 H.0 L.7 SALSEL CSSEL WRC BUSTYP CSSEL WRC SALSEL Port 4 ...

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Power reduction modes 21 Power reduction modes Three different power reduction modes with different levels of power reduction have been implemented in the ST10F272. In Idle mode only CPU is stopped, while peripheral still operate. In Power Down mode both ...

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ST10F272B/ST10F272E Before entering Power Down mode (by executing the instruction PWRDN), bit VREGOFF in XMISC register must be set. Note: Leaving the main voltage regulator active during Power Down may lead to unexpected behavior (ex: CPU wake-up) and power consumption ...

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Power reduction modes active: the portion of XRAM (16Kbytes for ST10F272E), the RTC counters and 32 kHz on- chip oscillator amplifier. In normal running mode (that is when main V during reset to exercise the EA functionality associated with the ...

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ST10F272B/ST10F272E Warning: 21.3.2 Exiting stand-by mode After the system has entered the Stand-by Mode, the procedure to exit this mode consists of a standard power-on sequence, with the only difference that the RAM is already powered through V internal reference ...

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Power reduction modes 21.3.4 Power reduction modes summary In Table 52, a summary of the different power reduction modes is reported. Table 52. Power reduction modes summary Mode Idle Powe own r d Stand-by 114/188 on on off on on ...

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ST10F272B/ST10F272E 22 Programmable output clock divider A specific register mapped on the XBUS allows to choose the division factor on the CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address range. When CLKOUT function is enabled by setting ...

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Register set 23 Register set This section summarizes all registers implemented in the ST10F272, ordered by name. 23.1 Special function registers Table 25 lists all SFRs which are implemented in the ST10F272 in alphabetical order. Bit-addressable SFRs are marked with ...

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ST10F272B/ST10F272E Table 53. List of special function registers (continued) Physical Name address CC4 FE88h CC4ICb FF80h CC5 FE8Ah CC5ICb FF82h CC6 FE8Ch CC6ICb FF84h CC7 FE8Eh CC7ICb FF86h CC8 FE90h CC8ICb FF88h CC9 FE92h CC9ICb FF8Ah CC10 FE94h CC10ICb FF8Ch ...

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Register set Table 53. List of special function registers (continued) Physical Name address CC21 FE6Ah CC21ICb F16AhE CC22 FE6Ch CC22ICb F16ChE CC23 FE6Eh CC23ICb F16EhE CC24 FE70h CC24ICb F170hE CC25 FE72h CC25ICb F172hE CC26 FE74h CC26ICb F174hE CC27 FE76h CC27ICb ...

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ST10F272B/ST10F272E Table 53. List of special function registers (continued) Physical Name address DP0Hb F102hE DP1Lb F104hE DP1Hb F106hE DP2 b FFC2h DP3 b FFC6h DP4 b FFCAh DP6 b FFCEh DP7 b FFD2h DP8 b FFD6h DPP0 FE00h DPP1 FE02h ...

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Register set Table 53. List of special function registers (continued) Physical Name address ODP7b F1D2hE ODP8b F1D6hE ONESb FF1Eh P0L b FF00h P0H b FF02h P1L b FF04h P1H b FF06h P2 b FFC0h P3 b FFC4h P4 b FFC8h ...

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ST10F272B/ST10F272E Table 53. List of special function registers (continued) Physical Name address PW1 FE32h PW2 FE34h PW3 FE36h PWMCON0b FF30h PWMCON1b FF32h PWMICb F17EhE QR0 F004hE QR1 F006hE QX0 F000hE QX1 F002hE RP0Hb F108hE S0BG FEB4h S0CONb FFB0h S0EICb FF70h ...

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Register set Table 53. List of special function registers (continued) Physical Name address T1 FE52h T1ICb FF9Eh T1REL FE56h T2 FE40h T2CONb FF40h T2ICb FF60h T3 FE42h T3CONb FF42h T3ICb FF62h T4 FE44h T4CONb FF44h T4ICb FF64h T5 FE46h T5CONb ...

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ST10F272B/ST10F272E Table 53. List of special function registers (continued) Physical Name address XPERCONb F024hE ZEROSb FF1Ch Note: 1. The system configuration is selected during reset. SYSCON reset value is 0000 0xx0 x000 0000b. 2. Reset Value depends on different triggered ...

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Register set Table 54. List of XBus registers (continued) Name CAN1IF2CM CAN1IF2CR CAN1IF2DA1 CAN1IF2DA2 CAN1IF2DB1 CAN1IF2DB2 CAN1IF2M1 CAN1IF2M2 CAN1IF2MC CAN1IP1 CAN1IP2 CAN1IR CAN1MV1 CAN1MV2 CAN1ND1 CAN1ND2 CAN1SR CAN1TR CAN1TR1 CAN1TR2 CAN2BRPER CAN2BTR CAN2CR CAN2EC CAN2IF1A1 CAN2IF1A2 CAN2IF1CM CAN2IF1CR CAN2IF1DA1 CAN2IF1DA2 ...

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ST10F272B/ST10F272E Table 54. List of XBus registers (continued) Name CAN2IF1MC CAN2IF2A1 CAN2IF2A2 CAN2IF2CM CAN2IF2CR CAN2IF2DA1 CAN2IF2DA2 CAN2IF2DB1 CAN2IF2DB2 CAN2IF2M1 CAN2IF2M2 CAN2IF2MC CAN2IP1 CAN2IP2 CAN2IR CAN2MV1 CAN2MV2 CAN2ND1 CAN2ND2 CAN2SR CAN2TR CAN2TR1 CAN2TR2 I2CCCR1 I2CCCR2 I2CCR I2CDR I2COAR1 I2COAR2 I2CSR1 I2CSR2 ...

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Register set Table 54. List of XBus registers (continued) Name RTCDH RTCDL RTCH RTCL RTCPH RTCPL XCLKOUTDIV XEMU0 XEMU1 XEMU2 XEMU3 XIR0CLR XIR0SEL XIR0SET XIR1CLR XIR1SEL XIR1SET XIR2CLR XIR2SEL XIR2SET XIR3CLR XIR3SEL XIR3SET XMISC XP1DIDIS XPEREMU XPICON XPOLAR XPP0 XPP1 ...

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ST10F272B/ST10F272E Table 54. List of XBus registers (continued) Name XPT2 XPT3 XPW0 XPW1 XPW2 XPW3 XPWMCON0 XPWMCON0CLR XPWMCON0SET XPWMCON1 XPWMCON1CLR XPWMCON1SET XPWMPORT XS1BG XS1CON XS1CONCLR XS1CONSET XS1PORT XS1RBUF XS1TBUF XSSCBR XSSCCON XSSCCONCLR XSSCCONSET XSSCPORT XSSCRB XSSCTB Physical Description address EC14h ...

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Register set 23.3 Flash registers ordered by name Table 55 lists all Flash Control Registers which are implemented in the ST10F272 ordered by their name. These registers are physically mapped on the IBus, except for XFVTAUR0, which is mapped on ...

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ST10F272B/ST10F272E IDMANUF (F07Eh / 3Fh Table 56. IDMANUF Bit Manufacturer identifier MANUF 020h: STMicroelectronics manufacturer (JTAG worldwide normalization). IDCHIP (F07Ch / 3Eh Table 57. IDCHIP Bit Device identifier IDCHIP 110h: ST10F272 identifier (272). Device ...

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Register set IDPROG (F078h / 3Ch Table 59. IDPROG Bit Programming V PROGVDD V DD following formula: V PROGVPP Programming V Note: All identification words are read only registers. The values written inside different Identification Register bits ...

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ST10F272B/ST10F272E 24 Electrical characteristics 24.1 Absolute maximum ratings Stressing the device above the rating listed in the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating ...

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Electrical characteristics 24.2 Recommended operating conditions Table 61. Recommended operating conditions Symbol V Operating supply voltage DD V Operationg stand-by supply voltage STBY V Operating analog reference voltage AREF T Ambient temperature under bias A T Junction temperature under bias ...

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ST10F272B/ST10F272E Table 62. Thermal characteristics Symbol Thermal Resistance Junction-Ambient PQFP 144 - 3 0.65 mm pitch Θ LQFP 144 - 0.5 mm pitch JA LQFP 144 - 20 x ...

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Electrical characteristics 24.5 DC characteristics ± 10 Table 64. DC characteristics Parameter Input low voltage (TTL mode) (except RSTIN, EA, NMI, RPD, XTAL1, READY) Input low voltage (CMOS mode) (except RSTIN, EA, NMI, RPD, ...

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ST10F272B/ST10F272E Table 64. DC characteristics (continued) Parameter Output high voltage (P6[7:0], ALE, RD, WR/WRL, BHE/WRH, CLKOUT, RSTOUT) (2) Output high voltage (P0[15:0], P1[15:0], P2[15:0], P3[15,13:0], P4[7:0], P7[7:0], P8[7:0]) Output high voltage RPD Input leakage current (P5[15:0]) Input leakage current (all ...

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Electrical characteristics Table 64. DC characteristics (continued) Parameter (12) Power Down supply current (RTC off, Oscillators off, Main Voltage Regulator off) (12) Power Down supply current (RTC on, Main Oscillator on, Main Voltage Regulator off) (12) Power Down supply current ...

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ST10F272B/ST10F272E 10. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is illustrated in the Figure 37 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with ...

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Electrical characteristics Figure 37. Supply current versus the operating frequency (RUN and IDLE modes) 138/188 Doc ID 11917 Rev 3 ST10F272B/ST10F272E ...

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ST10F272B/ST10F272E 24.6 Flash characteristics = 5 V ± 10 Table 65. Flash characteristics Parameter (2) Word Program (32-bit) (2)) Double Word Program (64-bit) Bank 0 Program (256K) (Double Word Program) Sector Erase (8K) Sector Erase (32K) Sector ...

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Electrical characteristics Table 66. Flash data retention characteristics Number of program / erase cycles (-40°C ≤ T ≤ 125° 100 1,000 10,000 100,000 1. Two 64Kbyte Flash Sectors may be typically used to emulate ...

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ST10F272B/ST10F272E Table 67. A/D converter characteristics Parameter 3) 8) Analog Switch Resistance 1. V can be tied to ground when A/D Converter is not in use: an extra consumption (around 200 AREF main V is added due to internal analogue ...

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Electrical characteristics Fast conversion can be achieved by programming the respective times to their absolute possible minimum. This is preferable for scanning high frequency signals. The internal resistance of analog source and analog supply must be sufficiently low, however. High ...

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ST10F272B/ST10F272E These four error quantities are explained below using Offset error Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage OFS). Gain error ...

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Electrical characteristics Figure 38. A/D conversion characteristic 24.7.4 Analog reference pins The accuracy of the A/D converter depends on how accurate is its analog reference: a noise in the reference results in at least that much error in a conversion. ...

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ST10F272B/ST10F272E besides, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter, can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC Filter). ...

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Electrical characteristics (sampled voltage on C must be designed to respect the following relation: Equation 1 The formula above provides a constraints for external network design, in particular on resistive path. A second aspect involving the capacitance network shall be ...

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ST10F272B/ST10F272E The charge voltage V on the capacitance according to the following equation: A1 Equation 4 ● A second charge transfer involves also C capacitance) through the resistance R and C were in parallel ...

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Electrical characteristics Figure 41. Anti-aliasing filter and conversion rate The considerations above lead to impose new constraints to the external circuit, to reduce the accuracy error due to the voltage drop on C above simple to derive the ...

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ST10F272B/ST10F272E Example of external network sizing The following hypothesis are formulated in order to proceed in designing the external network on A/D Converter input pins: ● Analog Signal Source Bandwidth (f ● conversion Rate (f ● Sampling Time (T ● ...

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Electrical characteristics Equation 14 5. Now the three element of the external circuit R conditions discussed in the previous paragraphs have been used to size the component, the other must now be verified. The relation which allow to minimize the ...

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ST10F272B/ST10F272E 24.8 AC characteristics 24.8.1 Test waveforms Figure 42. Input / output waveforms Note: AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’. Timing measurements are made at V Figure 43. ...

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Electrical characteristics The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5). Figure 44. Generation mechanisms for the CPU clock 24.8.3 Clock generation modes Table 69 associates the combinations of ...

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ST10F272B/ST10F272E accepted (minimum phase, high or low, again equal to 7.8ns). 3. The limits on input frequency are 4-8MHz since the usage of the internal oscillator amplifier is required. Also when the PLL is not used and the CPU clock ...

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Electrical characteristics 24.8.4 Prescaler operation When pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the internal oscillator (input clock signal 2:1 prescaler. The frequency of f the duration of an individual TCL) is ...

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ST10F272B/ST10F272E The reset default configuration enables the watchdog oscillator. It can be disabled by setting the OWDDIS (bit 4) of SYSCON register. When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the watchdog counter. ...

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Electrical characteristics Table 70. Internal PLL divider mechanism P0.15-13 XTAL (P0H.7-5) Frequency 8MHz 5.3 to 10.6MHz 8MHz 6.4 to 12MHz 0 1 ...

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ST10F272B/ST10F272E sufficiently large to have the long term jitter. For N=1, this becomes the single period jitter. Jitter at the PLL output can be due to the following reasons: ● Jitter in the input clock ● Noise in the PLL ...

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Electrical characteristics contribution of the digital noise to the global jitter is widely taken into account in the curves provided in Figure Figure 45. ST10F272 PLL jitter 24.8.10 PLL lock / unlock During normal operation, if the PLL gets unlocked ...

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ST10F272B/ST10F272E Table 71. PLL characteristics (V Symbol T PLL Start-up time PSUP T PLL Lock-in time LOCK Single Period Jitter T JIT (cycle to cycle = 2 TCL) F PLL free running frequency free 1. Not 100% tested, guaranteed by ...

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Electrical characteristics Table 73. Main oscillator negative resistance (module) C min. 545 Ω 4 MHz 240 Ω 8 MHz The given values of C printed circuit board: the negative resistance values are calculated assuming additional 5pF to the values in ...

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ST10F272B/ST10F272E Figure 47. 32kHz crystal oscillator connection diagram Table 75. Minimum values of negative resistance (module) for 32kHz oscillator C = 6pF A 32kHz - The given values of C printed circuit board: the negative resistance values are calculated assuming ...

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Electrical characteristics Table 76. External clock drive Parameter Symbol 1, 2 XTAL1 period t SR OSC 3 High time Low time Rise time Fall time ...

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ST10F272B/ST10F272E 24.8.15 External memory bus timing The following sections include the External Memory Bus timings. The given values are computed for a maximum CPU clock of 40MHz. Obviously, when higher CPU clock frequency is used (up to 64MHz), some numbers ...

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Electrical characteristics 24.8.16 Multiplexed bus ± 10 ALE cycle time = 6 TCL + 2t Table 78. Multiplexed bus timings Symbol Parameter t CC ALE high time Address setup to ALE 6 ...

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ST10F272B/ST10F272E Table 78. Multiplexed bus timings (continued) Symbol Parameter Latched CS low to Valid Data Latched CS hold after RD ALE fall. edge to RdCS, WrCS (with RW delay) ...

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Electrical characteristics Figure 49. External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE 166/188 Doc ID 11917 Rev 3 ST10F272B/ST10F272E ...

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ST10F272B/ST10F272E Figure 50. External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE Doc ID 11917 Rev 3 Electrical characteristics 167/188 ...

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Electrical characteristics Figure 51. External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS 168/188 Doc ID 11917 Rev 3 ST10F272B/ST10F272E ...

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ST10F272B/ST10F272E Figure 52. External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS Doc ID 11917 Rev 3 Electrical characteristics 169/188 ...

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Electrical characteristics 24.8.17 Demultiplexed bus ± 10 ALE cycle time = 4 TCL + 2t Table 79. Demultiplexed bus timings Symbol Parameter t CC ALE high time Address setup to ALE 6 ...

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ST10F272B/ST10F272E Table 79. Demultiplexed bus timings (continued) Symbol Parameter ALE falling edge to Latched Latched CS low to Valid Data Latched CS hold after RD Address setup to ...

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Electrical characteristics Figure 53. External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE 172/188 Doc ID 11917 Rev 3 ST10F272B/ST10F272E ...

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ST10F272B/ST10F272E Figure 54. Exteral memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE Doc ID 11917 Rev 3 Electrical characteristics 173/188 ...

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Electrical characteristics Figure 55. External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS 174/188 Doc ID 11917 Rev 3 ST10F272B/ST10F272E ...

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ST10F272B/ST10F272E Figure 56. External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS Doc ID 11917 Rev 3 Electrical characteristics 175/188 ...

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Electrical characteristics 24.8.18 CLKOUT and READY ± 10 Table 80. CLKOUT and READY timings Symbol Parameter t CC CLKOUT cycle time CLKOUT high time CLKOUT low time 31 t ...

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ST10F272B/ST10F272E Figure 57. CLKOUT and READY 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY sampled HIGH at this sampling point generates a ...

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Electrical characteristics 24.8.19 External bus arbitration = 5V ± 10 Table 81. External bus arbitration timings Symbol HOLD input setup time CLKOUT CLKOUT to HLDA high BREQ low delay ...

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ST10F272B/ST10F272E Figure 59. External bus arbitration (regaining the bus) 1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD ...

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Electrical characteristics 24.8.20 High-speed synchronous serial interface (SSC) timing 24.8.20.1 Master mode ±10 Table 82. SSC master mode timings Symbol Parameter t CC SSC clock cycle time 300 t CC SSC clock high time 301 ...

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ST10F272B/ST10F272E Figure 60. SSC master timing 1. The phase and polarity of shift and latch edge of SCLK is programmable. edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, ...

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Electrical characteristics Table 83. SSC slave mode timings (continued) Symbol Parameter Read data setup time before latch SR edge, phase error detection off t 317 (SSCPEN = 0) Read data hold time after latch SR edge, phase error detection off ...

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ST10F272B/ST10F272E 25 Package information To meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions, and product status are available at ECOPACK® trademark. ...

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Package information Figure 62. PQFP144 mechanical data and package dimension DIM. MIN. TYP 0.25 A2 3.17 B 0.22 C 0.13 D 30.95 31.20 D1 27.90 28.00 D3 22. 30.95 31.20 E1 27.90 28.00 E3 22.75 L ...

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ST10F272B/ST10F272E Figure 63. LQFP144 mechanical data and package dimension DIM. MIN. TYP 0.05 A2 1.35 B 0.17 C 0.09 D 22.00 D1 20.00 D3 17. 22.00 E1 20.00 E3 17. Note 1: ...

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Ordering information 26 Ordering information Table 84. Order codes Part number F272-BAR-P F272-BAR-P-TX F272-BAR-T F272-BAR-T-TX 186/188 Package Packing Type Tray PQFP144 Tape and reel Tray LQFP144 Tape and reel Doc ID 11917 Rev 3 ST10F272B/ST10F272E B/E Temperature CPU frequency range ...

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ST10F272B/ST10F272E 27 Revision history Table 85. Document revision history Date 02-November-2004 24-January-2005 29-August-2005 20-Jul-2006 12-Dec-2008 01-06-2012 Revision 0.7 Initial release. Chapter 4: CAN1 and CAN2 note about register access possibility updated (Page 19). Section 6.1: Decoding of P0L ...

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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any ...

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