SI4430-B1 SILABS [Silicon Laboratories], SI4430-B1 Datasheet
SI4430-B1
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SI4430-B1 Summary of contents
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... RF system designer to choose the optimal wireless part for their application. The Si4430/31/32’s high level of integration offers reduced BOM cost while simplifying the overall system design. The extremely low receive sensitivity (–121 dBm) coupled with industry leading +20 dBm output power ensures extended range and improved link performance ...
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... Si4430/31/32-B1 Functional Block Diagram 2 Rev 1.1 ...
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... Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.6. Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.7. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.8. Invalid Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.9. Synchronization Word Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.10. Receive Header Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.11. TX Retransmission and Auto Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.1. Modem Settings for FSK and GFSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Si4430/31/32-B1 Rev 1.1 Page 3 ...
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... Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12. Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 13. Pin Descriptions: Si4430/31/ 14. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 15. Package Markings (Top Marks 15.1. Si4430/31/32 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 15.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 16. Package Outline: Si4430/31/ 17. PCB Land Pattern: Si4430/31/ Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 4 Rev 1.1 ...
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... IGURES Figure 1. Si4430/31 RX/TX Direct-Tie Application Example ..................................................... 16 Figure 2. Si4432 Antenna Diversity Application Example ......................................................... 16 Figure 3. SPI Timing.................................................................................................................. 18 Figure 4. SPI Timing—READ Mode ..........................................................................................19 Figure 5. SPI Timing—Burst Write Mode .................................................................................. 19 Figure 6. SPI Timing—Burst Read Mode .................................................................................. 19 Figure 7. State Machine Diagram.............................................................................................. 20 Figure 8. TX Timing................................................................................................................... 24 Figure 9 ...
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... Table 12. Frequency Band Selection ....................................................................................... 26 Table 13. Packet Handler Registers ......................................................................................... 45 Table 14. Minimum Receiver Settling Time .............................................................................. 47 Table 15. POR Parameters ...................................................................................................... 50 Table 16. Temperature Sensor Range ..................................................................................... 53 Table 17. Antenna Diversity Control ......................................................................................... 60 Table 18. Register Descriptions ............................................................................................... 64 Table 19. Package Dimensions ................................................................................................ 69 Table 20. PCB Land Pattern Dimensions ................................................................................. 71 Si4430/31/32-B1 1 ...................................................................8 1 .......................................................................9 1 ................................................................. 10 1 ...................................................................................11 Rev 1.1 ...
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... Using Silicon Labs’ Reference Design. TX current consumption is dependent on match and board layout. txpow[2:0] = 010 (+1 dBm) Using Silicon Labs’ Reference Design. TX current consumption is dependent on match and board layout. Rev 1.1 Si4430/31/32-B1 Min Typ Max Units 1.8 3.0 3.6 V — ...
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... Si4430/31/32-B1 Table 2. Synthesizer AC Electrical Characteristics Parameter Symbol Synthesizer Frequency F SYN Range—Si4431/32 Synthesizer Frequency F SYN Range—Si4430 Synthesizer Frequency F RES-LB 2 Resolution F RES-HB Reference Frequency f REF_LV 2 Input Level 2 Synthesizer Settling Time t LOCK 2 F Residual FM RMS 2 Phase Noise L(f M Notes: 1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the " ...
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... GFSK with BT = 0.5, channel spacing = 150 kHz Desired Ref Signal 3 dB above sensitivity. Interferer and desired modulated with 40 kbps kHz GFSK with BT = 0.5 Rejection at the image frequency. IF=937 kHz Measured at RX pins Rev 1.1 Si4430/31/32-B1 Min Typ Max Units 240 — 930 MHz 900 — ...
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... OOK Modulation Deviation Δf1 Δf2 Modulation Deviation Δf RES 2 Resolution Output Power Range—Si4432 Output Power Range—Si4430/31 2 Output Steps RF_OUT 2 Output Level RF_TEMP Variation vs. Temperature Output Level RF_FREQ 2 Variation vs. Frequency Transmit Modulation B*T 2 ...
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... RES CT Using XTAL and board layout in reference design. Start-up time will vary with XTAL type and board layout. See "5.8. Crystal Oscillator" on RES page 40 for total load capacitance calculation RES Rev 1.1 Si4430/31/32-B1 Min Typ Max Units — 0.5 — °C — 5 — ...
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... Si4430/31/32-B1 Table 6. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) Parameter Symbol Rise Time T Fall Time T Input Capacitance Logic High Level Input Voltage Logic Low Level Input Voltage Input Current Logic High Level Output Voltage Logic Low Level Output Voltage Note: All specifications guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Power Amplifier may be damaged if switched on without proper load or termination connected. TX matching network design will influence TX V Parameter output pin. Caution: ESD sensitive device. RF-peak Rev 1.1 Si4430/31/32-B1 Value Unit –0.3, +3.6 V –0.3, +8.0 V –0.3, +6.5 V – ...
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... All RF input and output levels referred to the pins of the Si4430/31/32 (not the RF module) Qualification Test Conditions –40 to +85 °C +1.8 to +3.6 VDC DD Using TX/RX Split Antenna reference design or production test schematic All RF input and output levels referred to the pins of the Si4430/31/32 (not the RF module) MHz, centered around 0.8 VDC PP Rev 1.1 ...
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... Gaussian low-pass filter to reduce unwanted spectral content. The Si4432’s PA output power can be configured between +1 and +20 dBm steps, while the Si4430/31's PA output power can be configured between –8 and +13 dBm steps. The PA is single-ended to allow for easy antenna matching and low BOM cost ...
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... Si4430/31/32-B1 supply voltage C6 C7 100p 100n Figure 1. Si4430/31 RX/TX Direct-Tie Application Example Supply Voltage C6 100 p TR & ANT-DIV L3 Switch Figure 2. Si4432 Antenna Diversity Application Example 30MHz 1u VDD_RF RFp Si4430/ RXn ...
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... Operating Modes The Si4430/31/32 provides several operating modes which can be used to optimize the power consumption for a given application. Depending upon the system communication protocol, an optimal trade-off between the radio wake time and power consumption can be achieved. Table 9 summarizes the operating modes of the Si4430/31/32. In general, any given operating mode may be classified as an active mode or a power saving mode ...
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... Select high period SW To read back data from the Si4430/31/32, the R/W bit must be set to 0 followed by the 7-bit address of the register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored on the SDI pin when R The next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data read from the selected register will be available on the SDO output pin ...
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... SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI interface will automatically increment the ADDR and read from/write to the next address. An example burst write transaction is illustrated in Figure 5 and a burst read in Figure 6. As long as nSEL is held low, input data will be latched into the Si4430/31/32 every eight SCLK cycles. First Bit RW ...
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... Si4430/31/32-B1 3.2. Operating Mode Control There are four primary states in the Si4430/31/32 radio state machine: SHUTDOWN, IDLE, TX, and RX (see Figure 7). The SHUTDOWN state completely shuts down the radio to minimize current consumption. There are five different configurations/options for the IDLE state which can be selected to optimize the chip to the applications needs. " ...
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... This mode of operation is designed for frequency hopping spread spectrum systems (FHSS). TUNE mode is entered by setting pllon = 1 in "Register 07h. Operating Mode and Function Control 1" not necessary to set xton to 1 for this mode, the internal state machine automatically enables the crystal oscillator. Si4430/31/32-B1 Rev 1.1 21 ...
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... Si4430/31/32-B1 3.2.3. TX State The TX state may be entered from any of the IDLE modes when the txon bit is set "Register 07h. Operating Mode and Function Control 1". A built-in sequencer takes care of all the actions required to transition between states from enabling the crystal oscillator to ramping up the PA. The following sequence of events will occur automatically when going from STANDBY mode to TX mode by setting the txon bit ...
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... Interrupts The Si4430/31/32 is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers 03h– ...
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... Si4430/31/32-B1 3.4. System Timing The system timing for TX and RX modes is shown in Figures 8 and 9. The figures demonstrate transitioning from STANDBY mode mode through the built-in sequencer of required steps. The user only needs to program the desired mode, and the internal sequencer will properly transition the part from its current mode. ...
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... Frequency Programming In order to receive or transmit an RF signal, the desired channel frequency, f Si4430/31/32. The Si4431/32 and Si4430 cover different frequencies. This section discusses the frequency range covered by all EZRadioPRO devices. Note that this frequency is the center frequency of the desired channel and not an LO frequency. The carrier frequency is generated by a Fractional-N Synthesizer, using 10 MHz both as the reference frequency and the clock of the (3 accumulators ...
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... Si4430/31/32-B1 fb[4:0] Value The chip will automatically shift the frequency of the Synthesizer down by 937.5 kHz (30 MHz ÷ 32) to achieve the correct Intermediate Frequency (IF) when RX mode is entered. Low-side injection is used in the RX Mixing architecture ...
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... Easy Frequency Programming for FHSS While Registers 73h–77h may be used to program the carrier frequency of the Si4430/31/32 often easier to think in terms of “channels” or “channel numbers” rather than an absolute frequency value in Hz. Also, there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is desirable to change frequency by programming a single register. Once the channel step size is set, the frequency may be changed by a single register corresponding to the channel number. A nominal frequency is first set using Registers 73h– ...
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... Si4430/31/32-B1 The previous equation should be used to calculate the desired frequency deviation. If desired, frequency modulation may also be disabled in order to obtain an unmodulated carrier signal at the channel center frequency; see "4.1. Modulation Type" on page 32 for further details. Add R/W Function/Description 71 R/W Modulation Mode Control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] ...
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... PER) versus carrier offset and the impact of AFC are illustrated in Figure 11. Figure 11. Sensitivity at 1% PER vs. Carrier Frequency Offset set 156 . hbsel ) 1 fo DesiredOff set 156 . hbsel ) fo[7] fo[6] fo[5] fo[4] Rev 1.1 Si4430/31/32- POR Def. fo[3] fo[2] fo[1] fo[0] 00h fo[9] fo[8] 00h 29 ...
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... Si4430/31/32-B1 When AFC is enabled, the preamble length needs to be long enough to settle the AFC. In general, one byte of preamble is sufficient to settle the AFC. Disabling the AFC allows the preamble to be shortened from 40 bits to 32 bits. Note that with the AFC disabled, the preamble length must still be long enough to settle the receiver and to detect the preamble (see " ...
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... MHz txdr 15:0 DR_TX (bps) = -------------------------------------------------- - txdtrtscale 2 txdtrtscale DR_TX(bps) 2 txdr[15:0] = ------------------------------------------------------------------------------------- 1 MHz txdr[15] txdr[14] txdr[13] txdr[12] txdr[11] txdr[7] txdr[6] txdr[5] txdr[4] txdr[3] Rev 1.1 Si4430/31/32- POR Def. txdr[10] txdr[9] txdr[8] 0Ah txdr[2] txdr[1] txdr[0] 3Dh 31 ...
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... Modulation Options 4.1. Modulation Type The Si4430/31/32 supports three different modulation options: Gaussian Frequency Shift Keying (GFSK), Frequency Shift Keying (FSK), and On-Off Keying (OOK). GFSK is the recommended modulation type as it provides the best performance and cleanest modulation spectrum. Figure 12 demonstrates the difference between FSK and GFSK for a Data Rate of 64 kbps ...
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... Modulation Data Source The Si4430/31/32 may be configured to obtain its modulation data from one of three different sources: FIFO mode, Direct Mode, and from a PN9 mode. In Direct Mode, the TX modulation data may be obtained from several different input pins. These options are set through the dtmod[1:0] field in "Register 71h. Modulation Mode Control 2" ...
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... Si4430/31/32-B1 4.2.2. Direct Mode For legacy systems that perform packet handling within an MCU or other baseband chip, it may not be desirable to use the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely direct mode, the TX modulation data is applied to an input pin of the chip and processed in "real time" (i.e., not stored in a register for transmission at a later time) ...
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... TX/RX data clock. The SDI pin can be configured to be the data source in both RX and TX modes if dtmod[1: similar fashion, if nSEL is LOW the pin will function as SPI data-in. If nSEL is HIGH then in TX mode it will be the data to Si4430/31/32-B1 nIRQ nSEL Direct synchronous modulation ...
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... Si4430/31/32-B1 be modulated and transmitted mode it will be the received demodulated data. Figure 15 demonstrates using SDI and SDO as the TX/RX data and clock: nSEL SPI input don’t care SDI SPI output don’t care SDO Figure 15. Microcontroller Connections If the SDO pin is not used for data clock then it may be programmed to be the interrupt function (nIRQ) by programming Reg 0Eh bit 3 ...
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... Supported modulation types are GFSK, FSK, and OOK. The channel filter can be configured to support bandwidths ranging from 620 kHz down to 2.6 kHz. A large variety of data rates are supported ranging from 0.123 up to 256 kbps. The AGC algorithm is implemented digitally using an advanced control loop optimized for fast response time. ® features Rev 1.1 Si4430/31/32-B1 37 ...
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... An integrated Sigma Delta (ΣΔ) Fractional-N PLL synthesizer capable of operating from 240–960 MHz is provided on-chip. The Si4431/32 and Si4430 cover different frequencies. This section discusses the frequency range covered by all EZRadioPRO devices. Using a ΣΔ synthesizer has many advantages; it provides flexibility in choosing data rate, deviation, channel frequency, and channel spacing ...
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... Si4431/30 Output Power 000 –8 dBm 001 –5 dBm 010 –2 dBm 011 +1 dBm 100 +4 dBm 101 +7 dBm 110 +10 dBm 111 +13 dBm Rev 1.1 Si4430/31/32- txpow[1] txpow[0] POR Def. 18h 39 ...
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... Capacitance 5.9. Regulators There are a total of six regulators integrated onto the Si4430/31/32. With the exception of the digital regulator, all regulators are designed to operate with only internal decoupling. The digital regulator requires an external 1 µF decoupling capacitor. All regulators are designed to operate with an input supply voltage from +1.8 to +3.6 V. The output stage of the not connected internally to a regulator and is connected directly to the battery voltage ...
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... MCU time to process any interrupt signals that may have occurred. The host MCU must subsequently perform a WRITE to SPI Register 07h = 00h to enter STANDBY mode and obtain minimum current consumption. TX FIFO RX FIFO Figure 17. FIFO Thresholds Rev 1.1 Si4430/31/32-B1 RX FIFO Almost Full Threshold 41 ...
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... The fields needed for packet generation normally change infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload greatly reduces the amount of communication between the microcontroller and the Si4430/31/32 and reduces the required computational power of the microcontroller. ...
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... This w ill be sent in the first transm ission } This w ill be sent in the second transm ission } This w ill be sent in the third transm ission SYNC DATA RX FIFO Contents: rx_multi_pk_en = 0 rx_multi_pk_en = 1 txhdlen = 0 fixpklen 0 L Data Data Rev 1.1 Si4430/31/32-B1 txhdlen > 0 fixpklen Data Data Data 43 ...
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... Si4430/31/32-B1 Initial state FIFO Addr. RX FIFO Addr. Write Pointer L Data 63 63 Figure 22. Multiple Packets in RX with CRC or Header Error ERROR RX FIFO Addr. RX FIFO Addr Data Data Write Pointer Data Data ...
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... Rev 1.1 Si4430/31/32- POR Def. encrc crc[1] crc[0] crcerror pktx pksent hdch[3:0] synclen[1] synclen[0] prealen[8] prealen[2] prealen[1] prealen[0] rssi_off[2] rssi_off[1] ...
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... Figure 24. Manchester Coding Example 6.6. Preamble Detector The Si4430/31/32 has integrated automatic preamble detection. The preamble length is configurable from 1–255 bytes using the prealen[7:0] field in "Register 33h. Header Control 2" and "Register 34h. Preamble Length", as described in “6.2. Packet Configuration”. The preamble detection threshold, preath[4:0] as set in "Register 35h. ...
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... Registers 36h–39h. After preamble detection, the part will search for sync for a fixed Approximate Recommended Preamble Receiver Length with 8-Bit Settling Time Detection Threshold 1 byte 20 bits 2 byte 28 bits 1 byte — 2 byte — 2 byte 3 byte 8 byte — Rev 1.1 Si4430/31/32-B1 Recommended Preamble Length with 20-Bit Detection Threshold 32 bits 40 bits 64 bits 8 byte 4 byte 8 byte 47 ...
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... TX Retransmission and Auto TX The Si4430/31/32 is capable of automatically retransmitting the last packet loaded in the TX FIFO. Automatic retransmission is set by entering the TX state with the txon bit without reloading the TX FIFO. This feature is useful for beacon transmission or when retransmission is required due to the absence of a valid acknowledgement. Only packets that fit completely in the TX FIFO can be automatically retransmitted ...
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... The receiver data-rate, modulation index, and bandwidth are set via registers 1C–25h. The modulation index is equal to 2 times the peak deviation divided by the data rate (Rb). When Manchester coding is disabled, the required channel filter bandwidth is calculated 2Fd + Rb where Fd is the frequency deviation and Rb is the data rate. Si4430/31/32-B1 Rev 1.1 49 ...
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... Auxiliary Functions 8.1. Smart Reset The Si4430/31/32 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce a reliable reset signal under any circumstances. Reset will be initiated if any of the following conditions occur: Initial power on, VDD starts from gnd: reset is active till VDD reaches V ...
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... If the microcontroller clock option is being used there may be the need of a system clock for the microcontroller while the Si4430/31/ SLEEP mode. Since the crystal oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This feature is called enable low frequency clock and is enabled by the enlfc bit in “ ...
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... Si4430/31/32-B1 8.3. General Purpose ADC An 8-bit SAR ADC is integrated for general purpose use, as well as for digitizing the on-chip temperature sensor reading. Registers 0Fh "ADC Configuration", 10h "Sensor Offset" and 4Fh "Amplifier Offset" can be used to configure the ADC operation. Details of these registers are in “AN440: EZRadioPRO Detailed Register Descriptions.” ...
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... Unit 0 –64 … 64 °C 1 –64 … 192 ° … 128 °C 1 –40 … 216 ° … 341 °K Rev 1.1 Si4430/31/32- POR Def. 20h tstrim[2] vbgtrim[1] vbgtrim[0] 00h tvoffs[2] tvoffs[1] tvoffs[0] Slope ADC8 LSB 8 mV/°C 0.5 °C 4 mV/°C 1 ° ...
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... Si4430/31/32-B1 Temperature Measurement with ADC8 300 250 200 150 100 50 0 -40 -20 Figure 28. Temperature Ranges using ADC8 Temperature [Celsius] Rev 1.1 Sensor Range 0 Sensor Range 1 Sensor Range 2 Sensor Range 3 100 ...
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... lbdt[ vbat[4] vbat[3] vbat[2] vbat[1] vbat[0] tage ADCValue ADC Value VDD Voltage [V] 0 < 1.7 1 1.7–1.75 2 1.75–1.8 … … 29 3.1–3.15 30 3.15–3.2 31 > 3.2 Rev 1.1 Si4430/31/32- POR Def. lbdt[3] lbdt[2] lbdt[1] lbdt[0] 14h — 55 ...
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... Si4430/31/32-B1 8.6. Wake-Up Timer and 32 kHz Clock Source The chip contains an integrated wake-up timer which can be used to periodically wake the chip from SLEEP mode. The wake-up timer runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in SLEEP mode. If enwt = 1 in "Register 07h. Operating Mode and Function Control 1" when entering SLEEP mode, the wake-up timer will count for a time specified defined in Registers 14– ...
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... WUT Period GPIOX =00001 nIRQ SPI Interrupt Read Chip State Current Consumption Figure 29. WUT Interrupt and WUT Operation Interrupt Enable enwut =1 ( Reg 06h) Sleep Ready 1 Interrupt Enable enwut =0 ( Reg 06h) Sleep 1 uA Rev 1.1 Si4430/31/32-B1 Sleep Ready Sleep 1 ...
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... Si4430/31/32-B1 8.7. Low Duty Cycle Mode The Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is available. The basic operation of the low duty cycle mode is demonstrated in the figure below valid preamble or sync word is not detected the chip will return to sleep mode until the beginning of a new WUT period valid preamble and sync are detected the receiver on period will be extended for the low duty cycle mode duration (TLDC) to receive all of the packet ...
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... GPIO 00000—Default Setting GPIO0 POR GPIO1 POR Inverted GPIO2 Microcontroller Clock Rev 1.1 Si4430/31/32- POR Def. 00h 00h 00h dio2 dio1 dio0 00h 59 ...
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... Si4430/31/32-B1 8.9. Antenna Diversity To mitigate the problem of frequency-selective fading due to multi-path propagation, some transceiver systems use a scheme known as antenna diversity. In this scheme, two antennas are used. Each time the transceiver enters RX mode the receive signal strength from each antenna is evaluated. This evaluation process takes place during the preamble portion of the packet ...
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... Figure 31. RSSI Value vs. Input Power rssi[7] rssi[6] rssi[5] rssi[4] rssith[7] rssith[6] rssith[5] rssith[4] rssith[3] RSSI vs Input Power -80 -60 -40 In Pow [dBm] Rev 1.1 Si4430/31/32- POR Def. rssi[3] rssi[2] rssi[1] rssi[0] — rssith[2] rssith[1] rssith[0] 00h - ...
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... Si4430/31/32-B1 9. Reference Design Reference designs are available at schematics, BOM, and layout. TX matching component values for the different frequency bands can be found in the application notes “AN435: Si4032/4432 PA Matching” and “AN436: Si4030/4031/4430/4431 PA Matching.” RX matching component values for different frequency bands can be found in “AN427: EZRadioPRO Si433x and Si443x RX LNA Matching.” ...
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... AN436: Si4030/4031/4430/4431 PA Matching AN437: 915 MHz Measurement Results and FCC Compliance AN439: EZRadioPRO Quick Start Guide AN440: Si4430/31/32 Register Descriptions AN445: Si4431 RF Performance and ETSI Compliance Test Results AN451: Wireless M-BUS Software Implementation AN459: 950 MHz Measurement Results and ARIB Compliance ...
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... Si4430/31/32-B1 12. Register Table and Descriptions Add R/W Function/Desc 00 R Device Type 01 R Device Version 02 R Device Status 03 R Interrupt Status Interrupt Status 2 05 R/W Interrupt Enable 1 06 R/W Interrupt Enable 2 07 R/W Operating & Function Control 1 08 R/W Operating & Function Control 2 09 R/W Crystal Oscillator Load ...
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... Reserved Reserved Reserved txafthr[5] txafthr[4] Reserved Reserved txaethr[5] txaethr[4] Reserved Reserved rxafthr[5] rxafthr[4] fifod[7] fifod[6] fifod[5] fifod[4] Rev 1.1 Si4430/31/32-B1 Data pkvalid crcerror pktx hdch[3:0] fixpklen synclen[1] synclen[0] prealen[8] prealen[3] prealen[2] prealen[1] prealen[0] preath[0] rssi_off[2] rssi_off[1] rssi_off[0] sync[27] ...
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... PADDLE_GND GND The exposed metal paddle on the bottom of the Si4430/31/32 supplies the RF and circuit ground(s) for the entire chip very important that a good solder connection is made between this exposed metal paddle and the ground plane of the PCB underlying the Si4430/31/32. ...
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... Ordering Information Part Number* Si4430-B1-FM ISM EZRadioPRO Transceiver Si4431-B1-FM ISM EZRadioPRO Transceiver Si4432-B1-FM ISM EZRadioPRO Transceiver *Note: Add an “(R)” at the end of the device part number to denote tape and reel option. Si4430/31/32-B1 Description Rev 1.1 Package Operating Type Temperature QFN-20 – °C ...
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... Si4430/31/32-B1 15. Package Markings (Top Marks) 15.1. Si4430/31/32 Top Mark 15.2. Top Mark Explanation YAG Laser Mark Method Part Number Line 1 Marking Die Revision Line 2 Marking: TTTTT = Internal Code YY= Year Line 3 Marking Workweek Si4430 1 = Si4431 2 = Si4432 B = Revision B1 Internal tracking code. Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date ...
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... Package Outline: Si4430/31/32 Figure 33 illustrates the package details for the Si4430/31/32. Table 19 lists the values for the dimensions shown in the illustration. Figure 33. 20-Pin Quad Flat No-Lead (QFN) Symbol aaa bbb ccc ddd eee Notes: 1. All dimensions are shown in millimeters (mm) unless otherwise noted. ...
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... Si4430/31/32-B1 17. PCB Land Pattern: Si4430/31/32 Figure 34 illustrates the PCB land pattern details for the Si4430/31/32. Table 20 lists the values for the dimensions shown in the illustration. 70 Figure 34. PCB Land Pattern Rev 1.1 ...
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... A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be used for the center ground pad. Notes: Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for small body components. Rev 1.1 Si4430/31/32-B1 Millimeters Max 4.00 4.00 0.50 REF 0.30 2 ...
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... Si4430/31/32- OCUMENT HANGE IST Revision 0.4 to Revision 1.0 Combined 4430/4431/4432 into single data sheet. Added Max Shutdown and Standby Currents and adjusted typical values. Updated TX currents. Increased datarate to 256 kbps. Updated Table 11 on page 20. Revised "7. RX Modem Configuration" on page 49. ...
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... N : OTES Si4430/31/32-B1 Rev 1.1 73 ...
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... Si4430/31/32- ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...