saa2520 NXP Semiconductors, saa2520 Datasheet
saa2520
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saa2520 Summary of contents
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... DATA SHEET SAA2520 Stereo filter and codec for MPEG layer 1 audio applications Preliminary specification File under Integrated Circuits, IC01 INTEGRATED CIRCUITS August 1993 ...
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... V SS FDAC August 1993 GENERAL DESCRIPTION The SAA2520 performs the sub-band filtering and audio frame codec functions to provide efficient audio compression/decompression for MPEG (11172-3) Layer1 applications capable of functioning as a stand-alone decoder but requires the addition of an adaptive masking threshold processor (SAA2521) in order to function as a highly efficient encoder ...
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... AMPLIFIER DAC MICROCONTROLLER August 1993 1 SAA2520 Fig.2 Pin configuration. digital audio interface control SAA2520 system micro interface power down reset Fig.3 MPEG decoder system data flow diagram. 3 Preliminary specification SAA2520 LTCLK 33 32 LTDATA RESET DSC0 27 DSC1 ...
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... S clock, 6.144 MHz locked to FS256; 8 mA, 3-state output + CMOS 2 S direction: (FDAC, FDAF, SDA sync signal for SAA2521 2 S sub-band filter data; 4 mA, 3-state output + CMOS input with 2 S sub-band codec data; 4 mA, 3-state output + CMOS input with 4 Preliminary specification SAA2520 TYPE I I/O I/O I/O ...
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... MHz buffered output X22IN 40 22.5792 MHz crystal input X22OUT 41 22.5792 MHz crystal output X24IN 42 24.576 MHZ crystal input X24OUT 43 24.576 MHz crystal output V 44 positive supply voltage (+ August 1993 DESCRIPTION 5 Preliminary specification SAA2520 TYPE ...
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... SYNC AND CODING INFORMATION SCALING & QUANTIZATION quantized samples Fig.4 Encoding mode. CONTROL SCALE FACTOR ARRAY & ALLOCATION OUTPUT MULTIPLY DEQUANTIZATION CONTROL Fig.5 Decoding mode. 6 Preliminary specification SAA2520 FORMATTER MPEG OUTPUT DATA MLB128 sub-band samples base band SUB-BAND samples FILTER MLB129 ...
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... Adaptive Allocation functions of the SAA2521, this may change with every frame. The table is therefore calculated for each frame by the SAA2521 and then transferred to the SAA2520. A frame contains 2 384 samples of Left and Right audio data. This results in 12 samples per sub-band (32 sub-bands) ...
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... M X1 X22OUT X24IN 42 24.576 R4 MHz X24OUT Fig.6 Crystal oscillator components. left 32 bits 18 bits 13 bits LSB 2 8 Preliminary specification SAA2520 SAA2520 MLB130 right MLA923 - 2 MSB S default format). ...
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... LSB Fig.8 Transfer of SDA data (alternative format). left 32 bits 7 bits LSB Fig.9 Transfer of FDAF and FDAC (filtered) data. 9 Preliminary specification SAA2520 right MLA924 - 2 MSB right MLA925 - 2 ...
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... Philips Semiconductors Stereo filter and codec for MPEG layer 1 audio applications channel L SWS FSYNC sub-band Baseband Interface Signals The interface between the SAA2520 and the baseband input/output circuitry consists of the following signals: SWS bi-directional SCL bi-directional SDA bi-directional FDIR output The SWS signal indicates the channel of the sample signal (either LEFT or RIGHT) and is equal to the sampling frequency FS ...
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... Philips Semiconductors Stereo filter and codec for MPEG layer 1 audio applications Interface between SAA2520 and SAA2521 consists of the following signals ILTERED INTERFACE SWS bi-directional SCL bi-directional FDAC bi-directional FDAF bi-directional FSYNC output Filtered data is transferred between SAA2520 filter/codec functions and the SAA2521 using the format shown in Fig ...
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... August 1993 request a general reset of SAA2521 '1' for decoding and '0' for encoding mode (common to I pulse for synchronization of digital input/output (TDA1315) (kHz Preliminary specification SAA2520 SBCL FREQUENCY (kHz) 768 512 384 256 2 S) ...
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... SDA, FDAF, FDAC output valid August 1993 81.4 ns nominal 88.6 ns nominal 122.1 ns nominal 4T ns nominal Preliminary specification SAA2520 MEA642 - 3 ...
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... SCL HIGH August 1993 interface timing (slave mode - FS256, SCL and SWS are input). 14 Preliminary specification SAA2520 MEA644 - ...
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... HIGH Z SWS HIGH Z HIGH Z FS256 SCL HIGH Z HIGH Z FDAF FDAC Fig.13 Mode switch timing. 300 ns 1280 ns 790 170 170 Preliminary specification SAA2520 HIGH Z SDA t d9 SWS FS256 SCL MEA646 - 1 ...
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... SYNCDAI HIGH t FS256, SWS, SCL remain HIGH D9 impedance after SYNCDAI HIGH SBWS SBCL 1 SBDA bit : MSB SBEF Fig.14 Transferring MPEG data to and from the SAA2520. August 1993 460 ns 140 ns 140 ns 32 bits 15 bits ...
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... Notes 1. During encoding the SBEF signal is ‘don’t care’. 2. Incoming data is not decoded. The SAA2520 operates in the encoding mode and the data does not enter the interface. 3. Operation is undefined. The SAA2520 is in decoding mode whilst the SBWS, SBCL and SBDA output drivers are enabled ...
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... August 1993 120 to 205 ns (163 ns nominal nominal 12T ns nominal 16T ns nominal 24T ns nominal 12T - 12T - Preliminary specification SAA2520 MEA645 - 2 ...
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... su1 t h1 SBWS SBDA t h2 SBEF t su2 S interface timing (slave mode - SBCL, SBWS and SBDA are input). 6.86T to 96T ns (8T ns nominal 2T Preliminary specification SAA2520 MEA648 - 2 ...
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... Notes to Fig.17 t SBDIR HIGH to SBCL, SBWS, SBDA high impedance D1 t SBCL, SBWS, SBDA after SBDIR LOW high impedance D2 August 1993 HIGH Z 2 Fig.17 Sub-band I S mode switch timing. 20 Preliminary specification SAA2520 SBDIR t d2 SBCL HIGH Z SBWS SBDA MEA647 - 240 ns ...
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... Philips Semiconductors Stereo filter and codec for MPEG layer 1 audio applications Microcontroller interface The SAA2520 has an interface connection to the serial interface of a microcontroller. The following signals are used: LTCLK input LTDATA bi-directional LTCNT0 input LTCNT1 input LTENA input The SAA2520 microcontroller interface is enabled only if LTENA (pin 34) is logic 1 ...
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... After the first transfer of allocation information a check must be made to determine when the SAA2520 is ready to receive the remaining information. This will ensure synchronization with the internal program of the SAA2520. Transfer of the allocation information is completed by sending the internal settings. Table 6 Allocation information format. ...
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... The decode bit determines the operation mode of the SAA2520. The default value is logic 1 (decoding mode). EXT 256FS in the encoding mode determines whether or not the SAA2520 is master or slave of the Filtered-I interface (default is logic 0, master mode). 2CH MONO is used in the encoding mode to determine whether the sub-band signal is generated as a stereo or 2-channel mono signal ...
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... Table 11 EMPHASIS indication. msb Before sending internal settings the microcontroller should check whether or not the SAA2520 is ready-to-receive. However, this does not apply for the transfer of internal settings to end a transfer of allocation information. S (LTCNT = 1, LTNCT0 = TATUS LOGIC Table 12 Status information 16-bit units. ...
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... The same occurs with all samples in 1-channel mono decode mode. In both of these instances the L and R filter output channels are identical. In decode mode the SYNC bit is logic 0 when the SAA2520 is unable to decode the sub-band frames. This will occur in the following situations: with the loss of synchronisation when in correct allocation information is received for two or more subsequent frames (SBEF was HIGH) ...
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... Stereo filter and codec for MPEG layer 1 audio applications handbook, full pagewidth LTENA LTCNT0/1 LTCLK LTDATA Fig.18 Transfer of data on SAA2520 microcontroller interface. handbook, full pagewidth LTENA 16 bits allocation / scale factor information LTCLKC Fig.19 The LTENA line must return to logic 0 between information transfers. August 1993 ...
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... Philips Semiconductors Stereo filter and codec for MPEG layer 1 audio applications handbook, full pagewidth LTENA LTCNT0/1 LTCLK LTDATA bit : Fig.20 Order of settings and status bits on the SAA2520 microcontroller interface. handbook, full pagewidth LTENA LTCNT0/1 LTCLK LTDATA OUTPUT 8 t delay LTCLK HIGH to LTDATA valid output for bit 0 in 16-bit transfers ...
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... LTENA hold after LTCLK HIGH H4 August 1993 LTCNT0 LTCNT1 Fig.22 Microcontroller interface timing. 28 Preliminary specification SAA2520 hiZ MLB135 190 ns 190 ns 190 ns 190 380 355 ns 190 ns 355 ns 520 ns 190 ns ...
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... (note 3.8 V (note amb amb 0. amb 29 Preliminary specification SAA2520 MIN. MAX. 0.5 6.5 0 0.5 DD 160 160 880 55 150 - 40 85 1500 1500 70 70 MIN. TYP. MAX. 5.0 5.5 82 110 ...
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... amb + 0 0. amb 30 Preliminary specification SAA2520 TYP. MAX. UNIT 0. 1.5 V 250 250 250 0.3V ...
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... A = gm.R 3 kHz 81 44.1 kHz 88 kHz 122 Preliminary specification SAA2520 TYP. MAX. UNIT MHz 26 MHz mA/V V ...
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... T+35 T+35 2T-15 20 T+20 120 163 Preliminary specification SAA2520 TYP. MAX. UNIT 3T+ 205 ...
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... SBCL LOW 20 after SBCL 0 note 2 6.86T before SBCL HIGH after SBCL 30 HIGH after SBCL HIGH after SBCL 2T 30 HIGH 33 Preliminary specification SAA2520 TYP. MAX. UNIT 96T ...
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... scale (1) ( 0.25 14.1 14.1 19.2 19.2 1 2.35 0.14 13.9 13.9 18.2 18.2 REFERENCES JEDEC EIAJ 34 Preliminary specification SAA2520 SOT205 detail X (1) ( 2.0 2.4 2.4 7 0.3 0.15 0.1 o 1.2 1.8 1.8 0 EUROPEAN ISSUE DATE PROJECTION 95-02-04 97-08-01 3 ...
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... Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 35 Preliminary specification SAA2520 ...
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... Philips customers using or selling these products for use in such applications their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1993 36 Preliminary specification SAA2520 ...