mx25l1605zmi-20g Macronix International Co., mx25l1605zmi-20g Datasheet
mx25l1605zmi-20g
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mx25l1605zmi-20g Summary of contents
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FEATURES GENERAL • Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3 • 16,777,216 x 1 bit structure • 32 Equal Sectors with 64K byte each - Any sector can be erased • Single Power Supply Operation - ...
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GENERAL DESCRIPTION The MX25L1605 is a CMOS 16,777,216 bit serial eLiteFlash TM Memory, which is configured as 2,097,152 x 8 internally. The MX25L1605 features a serial peripheral interface and software protocol allowing operation on a simple 3- wire bus. The ...
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BLOCK DIAGRAM Generator SI CS#, ACC, WP#,HOLD# SCLK P/N: PM1291 MX25L1605ZM Address Memory Array Data Register Y-Decoder SRAM Buffer Mode State HV Logic Machine Generator Clock Generator 3 Output Sense Amplifier Buffer SO REV. 1.0, MAY 16, 2006 ...
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DATA PROTECTION • Power-On Reset and an internal timer (tPUW) can provide protection against inadvertant changes while the power supply is outside the operating specification. • Program, Erase and Write Status Register instructions are checked that they consist of a ...
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Table 1. Protected Area Sizes Status bit BP2 BP1 BP0 Note: 1. The device is ready ...
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HOLD FEATURE HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select(CS#) keeping ...
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Table 2. COMMAND DEFINITION COMMAND WREN WRDI (byte) (write (write Enable) disable) 1st 06 Hex 04 Hex 2nd 3rd 4th 5th Action sets the reset the output the (WEL) (WEL) write write enable enable latch bit latch bit COMMAND SE ...
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Sector Address Range 31 1F0000h 30 1E0000h 29 1D0000h 28 1C0000h 27 1B0000h 26 1A0000h 25 190000h 24 180000h 23 170000h 22 160000h 21 150000h 20 140000h 19 130000h 18 120000h 17 110000h 16 100000h P/N: PM1291 MX25L1605ZM Sector 1FFFFFh ...
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DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby ...
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COMMAND DESCRIPTION (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, CE, and WRSR, which are intended to change the device content, should be set every ...
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Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously recommended to check the Write in ...
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Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ...
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Note: If SRWD bit=1 but WP# is low impossible to write the Status Register even if the WEL bit has previously been set rejected to write the Status Register and not be executed. Hardware Protected Mode ...
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Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector ...
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Enter 4Kbit Mode (EN4K) and Exit 4Kbit Mode (EX4K) Enter and Exit 4kbit mode (EN4K & EX4K) (see Figure 27 & 28) EN4K and EX4K will not be executed when the chip is in busy state. Enter 4kbit mode ...
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SCLK while CS low. If the device was not previously in Deep Power- down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down ...
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POWER-ON STATE P/N: PM1291 MX25L1605ZM 17 REV. 1.0, MAY 16, 2006 ...
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature - for Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential Figure 4.Maximum Negative Overshoot Waveform 20ns 0V -0.5V CAPACITANCE ...
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Figure 6. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing referance level 0.8VCC 0.2VCC Figure 7. OUTPUT LOADING DEVICE UNDER TEST P/N: PM1291 MX25L1605ZM Output timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time ...
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Table 5. DC CHARACTERISTICS (Temperature = - for Industrial grade, Temperature = SYMBOL PARAMETER ILI Input Load Current ILO Output Leakage Current ISB1 VCC Standby Current ISB2 Deep Power-down Current ICC1 VCC Read ICC2 VCC Program ...
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Table 6. AC CHARACTERISTICS (Temperature = - for Industrial grade, Temperature = Symbol Alt. Parameter fSCLK fC Clock Frequency for the following instructions: FAST_READ, PP, SE, BE, DP, RES,REMS, RDP WREN, WRDI, RDID, RDSR, WRSR, EN4K, ...
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Table 7. Power-Up Timing and VWI Threshold Symbol Parameter tVSL(1) VCC(min low tPUW(1) Time delay to Write instruction VWI(1) Write Inhibit Voltage Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the ...
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Figure 8. Serial Input Timing CS# tCHSL SCLK tDVCH SI High Impedance SO Figure 9. Write Protect Setup and Hold Timing during WRSR when SRWD=1 WP# tWHSL CS# SCLK SI High Impedance SO P/N: PM1291 MX25L1605ZM tSLCH tCHSH tCHDX tCLCH ...
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Figure 10. Hold Timing CS# SCLK SO SI HOLD# Figure 11. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1291 MX25L1605ZM tHLCH tCHHL tHHCH tCHHH tHLQZ tHHQX tCH tCLQV tCL tQLQH tQHQL 24 tSHQZ LSB OUT ...
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Figure 12. Write Enable (WREN) Instruction Sequence CS# SCLK SI SO Figure 13. Write Disable (WRDI) Instruction Sequence CS# SCLK SI SO Figure 14. Read Identification (RDID) Instruction Sequence and Data-Out Sequence CS SCLK Instruction SI High ...
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Figure 15. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence CS SCLK Instruction SI High Impedance SO Notes: In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That ...
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Figure 18. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence CS SCLK Instruction SI High Impedance SO CS SCLK Notes: In READ mode, FAST_READ mode, RES ...
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Figure 19. Page Program (PP) Instruction Sequence CS SCLK Instruction SI CS SCLK Data Byte MSB Figure 20. Sector Erase ...
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Figure 21. Chip Erase (CE) Instruction Sequence CS# SCLK SI Note: CE instruction is 60(hex) or C7(hex). Figure 22. Deep Power-down (DP) Instruction Sequence CS# 0 SCLK SI Figure 23. Release from Deep Power-down and Read Electronic Signature (RES) Instruction ...
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Figure 24. Release from Deep Power-down (RDP) Instruction Sequence CS SCLK SI High Impedance SO Figure 25. Read Electronic Manufacturer & Device ID (REMS) Instruction Sequence and Data-Out Sequence CS SCLK Instruction SI High ...
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Figure 26. Power-up Timing (max) Program, Erase and Write Commands are Rejected by the Device V CC (min) Reset State of the Device V WI P/N: PM1291 MX25L1605ZM Chip Selection Not Allowed tVSL Read Access allowed ...
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Figure 27. Enter 4Kbit Mode (EN4K) Instruction Sequence CS# SCLK SI SO Figure 28. Exit 4Kbit Mode (EX4K) Instruction Sequence CS# SCLK SI SO Note: Enter and Exit 4kbit mode (EN4K & EX4K) EN4K and EX4K will not be executed ...
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Figure 29. READ ARRAY WAVEFORM (Parallel) NOTES: 1. 1st Byte='03h' 2. 2nd Byte=Address 1(AD1), AD23=BIT7, AD22=BIT6, AD21=BIT5, AD20=BIT4,....AD16=BIT0. 3. 3rd Byte=Address 2(AD2), AD15=BIT7, AD14=BIT6, AD13=BIT5, AD12=BIT4,....AD8=BIT0. 4. 4th Byte=Address 3(AD3), AD7=BIT7, AD6=BIT6, ....AD0=BIT0. 5. From Byte 5, SO Would Output ...
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Figure 30. AUTO PAGE PROGRAM TIMING WAVEFORM (Parallel) NOTES: 1. 1st Byte='02h' 2. 2nd Byte=Address 1(AD1), AD23=BIT7, AD22=BIT6, AD21=BIT5, AD20=BIT4,....AD16=BIT0. 3. 3rd Byte=Address 2(AD2), AD15=BIT7, AD14=BIT6, AD13=BIT5, AD12=BIT4,....AD8=BIT0. 4. 4th Byte=Address 3(AD3), AD7=BIT7, AD6=BIT6, ....AD0=BIT0. 5. 5th byte: 1st write ...
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Figure 31. Read Identification (RDID) Instruction Sequence and Data-Out Sequence (Parallel) CS SCLK Instruction SI High Impedance PO7~0 NOTES: 1. Under parallel mode, the fastest access clock freg. will be changed to 1.2MHz(SCLK pin clock freg.) ...
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Figure 32. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and Data-Out Sequence (Parallel) CS SCLK Instruction SI High Impedance PO7~0 NOTES: 1. Under parallel mode, the fastest access clock freg. ...
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Figure 33. READ STATUS REGISTER TIMING WAVEFORM (Parallel) NOTES: 1. 1st Byte='05h' 2. BIT7 status register write disable signal. BIT7=1, means SR write disable. 3. BIT6=0 ==> Program/erase is correct. 4. BIT4 defines the level of protected block. ...
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Figure 34. Read Electronic Manufacturer & Device ID (REMS) Instruction Sequence and Data-Out Sequence (Parallel) CS SCLK Instruction SI High Impedance PO7~0 CS# SCLK PO7~0 NOTES: (1) ADD=00H will output the manufacturer's ...
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RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) ...
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ERASE AND PROGRAMMING PERFORMANCE PARAMETER Chip Erase Time Chip Erase Time (with ACC=12V) Sector erase Time Sector erase Time (with ACC=12V) Additional 4Kb Erase Time Page Programming Time Page Programming Time (with ACC=12V) Erase/Program Main Array Cycle Additional 4Kb Note: ...
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... ORDERING INFORMATION PART NO. ACCESS TIME(ns) MX25L1605ZMC-20G 20 MX25L1605ZMI-20G 20 P/N: PM1291 MX25L1605ZM OPERATING STANDBY CURRENT(mA) CURRENT(uA Temperature PACKAGE Remark 0~70 C 8-land SON Pb-free -40~85 C 8-land SON Pb-free REV. 1.0, MAY 16, 2006 ...
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PART NAME DESCRIPTION 1605 P/N: PM1291 MX25L1605ZM OPTION: G: Pb-free blank: normal SPEED: 20: 50MHz, for SPI TEMPERATURE RANGE: C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: ZM: SON DENSITY ...
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PACKAGE INFORMATION P/N: PM1291 MX25L1605ZM 43 REV. 1.0, MAY 16, 2006 ...
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... MX25L1605ZM MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...