mx25l12805d Macronix International Co., mx25l12805d Datasheet
mx25l12805d
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mx25l12805d Summary of contents
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... Status Register Feature • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte Device ID - RES command, 1-byte Device ID - REMS command, ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first P/N: PM1310 MX25L12805D 128M-BIT [x 1] CMOS SERIAL FLASH 1 REV. 1.1, OCT. 01, 2008 ...
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... Serial access to the device is enabled by CS# input. The MX25L12805D provides sequential read operation on whole chip. User may start to read from any byte of the array. While the end of the array is reached, the device will wrap around to the beginning of the array and continuously outputs data until CS# goes high ...
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... GND CS WP#/ACC P/N: PM1310 MX25L12805D PIN DESCRIPTION SYMBOL DESCRIPTION CS# Chip Select SI Serial Data Input SO Serial Data Output SCLK Clock Input HOLD# Hold, to pause the serial communication WP#/ACC Write Protection: connect to GND; 11V for program/erase acceleration: ...
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... BLOCK DIAGRAM Address Generator SI Register CS#, ACC, WP#,HOLD# SCLK Clock Generator P/N: PM1310 MX25L12805D Memory Array Data Y-Decoder SRAM Buffer Mode State HV Logic Machine Generator 4 Sense Output Buffer Amplifier SO REV. 1.1, OCT. 01, 2008 ...
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... DATA PROTECTION The MX25L12805D are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences ...
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... Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512-bit secured OTP mode, array access is not allowed. 512-bit Secured OTP Definition Address range Size xxxx00~xxxx0F 128-bit xxxx10~xxxx3F 384-bit P/N: PM1310 MX25L12805D Standard Factory Lock ESN (electrical serial number) Determined by customer N/A 6 Customer Lock REV. 1.1, OCT. 01, 2008 ...
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... Note: 1. The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0. P/N: PM1310 MX25L12805D Protection Area 128Mb All All All All All All All Upper half (hundrend and twenty-eight sectors: 128 to 255) ...
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... AND PROGRAM PERFORMACE". Figure 2. ACCELERATED PROGRAM TIMING DIAGRAM V HH 11V ACC t VHH Note: tVHH (VHH Rise and Fall Time) min. 250ns P/N: PM1310 MX25L12805D Hold Hold Condition Condition (standard) (non-standard VHH ...
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... OTP mode secured OTP mode Note not recommoded to adopt any other code not in the command definition table, which will potentially emter the hidden mode. P/N: PM1310 MX25L12805D RDID (read RDSR (read WRSR (write identification) status ...
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... FAF000h FAFFFFh 250 4000 FA0000h FA0FFFh 95 05F000h 5 80 050000h 79 04F000h 4 64 040000h 63 03F000h 3 48 030000h 47 02F000h 2 32 020000h 31 01F000h 1 16 010000h 15 00F000h 0 0 000000h P/N: PM1310 MX25L12805D 05FFFFh 050FFFh 04FFFFh 040FFFh 03FFFFh 030FFFh 02FFFFh 020FFFh 01FFFFh 010FFFh 00FFFFh 000FFFh 10 REV. 1.1, OCT. 01, 2008 ...
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... CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1310 MX25L12805D MSB 11 MSB REV. 1.1, OCT. 01, 2008 ...
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... RDID operation can use CS# to high at any time during data out. (see Figure. 14) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. P/N: PM1310 MX25L12805D 12 REV. 1.1, OCT. 01, 2008 ...
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... Status reserved the level of the level of the level of the level of Register Write protected Protect block 1= status register write (note 1) disable Note: 1. see the table "Protected Area Sizes". P/N: PM1310 MX25L12805D bit 4 bit 3 bit 2 BP2 BP1 BP0 protected protected protected block block block ...
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... When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0 software protected mode (SPM) P/N: PM1310 MX25L12805D WP# and SRWD bit status WP#=1 and SRWD bit=0, or ...
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... Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS# goes high. (see Figure 20) P/N: PM1310 MX25L12805D 15 REV. 1.1, OCT. 01, 2008 ...
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... If less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low-> sending PP instruction code-> 3-byte address on SI-> at least P/N: PM1310 MX25L12805D 16 REV. 1.1, OCT. 01, 2008 ...
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... CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode. P/N: PM1310 MX25L12805D 17 REV. 1.1, OCT. 01, 2008 ...
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... Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 512-bit secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low-> sending EXSO instruction to exit Secured OTP mode-> CS# goes high. P/N: PM1310 MX25L12805D memory type C2 20 electronic ID 17 ...
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... Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low-> sending WRSCUR instruction -> CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. P/N: PM1310 MX25L12805D bit4 bit3 bit2 x ...
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... At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress. P/N: PM1310 MX25L12805D 20 REV. 1.1, OCT. 01, 2008 ...
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... Figure 4.Maximum Negative Overshoot Waveform 20ns 0V -0.5V CAPACITANCE TA = 25° ° ° ° ° 1.0 MHz SYMBOL PARAMETER CIN Input Capacitance COUT Output Capacitance P/N: PM1310 MX25L12805D VALUE -40° 85° C for Industrial grade -55° 125° C -0.5V to 4.6V -0.5V to 4.6V -0.5V to 4.6V Figure 5. Maximum Positive Overshoot Waveform 4.6V 3.6V MIN. TYP MAX ...
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... Figure 6. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing referance level 0.8VCC 0.2VCC Figure 7. OUTPUT LOADING DEVICE UNDER TEST P/N: PM1310 MX25L12805D Output timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time are <5ns 2.7K ohm CL 6.2K ohm DIODES=IN3064 ...
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... Input High Voltage VOL Output Low Voltage VOH Output High Voltage NOTES: 1. Typical values at VCC = 3.3V 25° C. These currents are valid for all product versions (package and speeds). 2. Typical value is calculated by simulation. P/N: PM1310 MX25L12805D MIN. TYP MAX. UNITS ± ± ...
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... Chip Erase Cycle Time Notes: 1. tCH + tCL must be greater than or equal Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set Test condition is shown as Figure 5. P/N: PM1310 MX25L12805D Min. Typ. 10K 10K 7 7 0.1 ...
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... Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1310 MX25L12805D Min. Max. 200 1 1 ...
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... Figure 8. Serial Input Timing CS# tCHSL SCLK tDVCH SI High-Z SO Figure 9. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1310 MX25L12805D tSLCH tCHSH tCHDX tCLCH MSB LSB tCH tCLQV tCL tQLQH tQHQL 26 tSHSL tSHCH tCHCL tSHQZ LSB REV. 1.1, OCT. 01, 2008 ...
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... Figure 10. Hold Timing CS# SCLK SO HOLD "don't care" during HOLD operation. Figure 11. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tWHSL CS SCLK SI High-Z SO P/N: PM1310 MX25L12805D tHLCH tCHHL tCHHH tHLQZ tHHCH tHHQX tSHWL 11 12 ...
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... Figure 12. Write Enable (WREN) Sequence (Command 06) CS# SCLK SI SO Figure 13. Write Disable (WRDI) Sequence (Command 04) CS# SCLK SI SO Figure 14. Read Identification (RDID) Sequence (Command 9F) CS SCLK Command SI High-Z SO P/N: PM1310 MX25L12805D Command 06 High Command ...
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... Figure 16. Write Status Register (WRSR) Sequence (Command 01) CS# SCLK SI SO Figure 17. Read Data Bytes (READ) Sequence (Command 03) CS SCLK command 03 SI High-Z SO P/N: PM1310 MX25L12805D Status Register Out MSB ...
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... Figure 18. Read Data Bytes at Higher Speed (FAST_READ) Sequence (Command 0B) CS SCLK Command SI 0B High SCLK Dummy Byte P/N: PM1310 MX25L12805D BIT ADDRESS ...
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... CS SCLK Data Byte MSB Figure 20. Sector Erase (SE) Sequence (Command 20) CS# SCLK SI Note: SE command is 20(hex). P/N: PM1310 MX25L12805D 24-Bit Address MSB MSB ...
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... Figure 21. Block Erase (BE) Sequence (Command D8) CS# SCLK SI Note: BE command is D8(hex). Figure 22. Chip Erase (CE) Sequence (Command 60 or C7) CS# SCLK SI Note: CE command is 60(hex) or C7(hex). Figure 23. Deep Power-down (DP) Sequence (Command B9) CS SCLK SI P/N: PM1310 MX25L12805D Command 24 Bit Address MSB 0 ...
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... SCLK Command SI AB High-Z SO Figure 25. Release from Deep Power-down (RDP) Sequence (Command AB) CS SCLK SI High-Z SO P/N: PM1310 MX25L12805D Dummy Bytes MSB Electronic Signature Out MSB Deep Power-down Mode ...
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... SCLK Command SI 90 High-Z SO CS# SCLK ADD ( Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first (2) Instruction is 90(hex). P/N: PM1310 MX25L12805D Dummy Bytes ...
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... Figure 27. Power-up Timing (max) Program, Erase and Write Commands are Ignored V CC (min) Reset State of the Flash V WI P/N: PM1310 MX25L12805D Chip Selection is Not Allowed tVSL Read Command is tPUW 35 Device is fully allowed accessible time REV. 1.1, OCT. 01, 2008 ...
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... VCC Rise Time Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1310 MX25L12805D tCHSL tSLCH tDVCH tCHDX MSB IN High Impedance Figure A. AC Timing at Device Power-Up ...
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... Input Voltage with respect to GND on ACC Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1310 MX25L12805D Min. TYP. (1) Max. (2) 40 100 ...
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... ORDERING INFORMATION PART NO. SERIAL CLOCK RATE MX25L12805DMI-20G 50MHz P/N: PM1310 MX25L12805D READ STANDBY Temperature PACKAGE CURRENT(max.) CURRENT(max.) 25mA 20uA 38 Remark -40~85°C 16-SOP Pb-free REV. 1.1, OCT. 01, 2008 ...
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... PART NAME DESCRIPTION P/N: PM1310 MX25L12805D 12805D OPTION: G: Pb-free SPEED: 20: 50MHz TEMPERATURE RANGE: I: Industrial (-40˚C to 85˚C) PACKAGE: M: 300mil 16-SOP DENSITY & MODE: 12805D: 128Mb TYPE DEVICE: 25: Serial Flash 39 REV. 1.1, OCT. 01, 2008 ...
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... PACKAGE INFORMATION P/N: PM1310 MX25L12805D 40 REV. 1.1, OCT. 01, 2008 ...
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... REVISION HISTORY Revision No. Description 1.0 Removed "Advanced Information" on page 1 1.1 Revised sector erase time spec from 90ms(typ.) to 60ms(typ.) P/N: PM1310 MX25L12805D Page P1 P24,37 41 Date FEB/26/2008 OCT/01/2008 REV. 1.1, OCT. 01, 2008 ...
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... Tel: +81-44-246-9100 Fax: +81-44-246-9105 Macronix (Hong Kong) Co., Limited. 702-703, 7/F, Building 9, Hong Kong Science Park, 5 Science Park West Avenue, Sha Tin, N.T. Tel: +86-852-2607-4289 Fax: +86-852-2607-4229 http : //www.macronix.com MX25L12805D C L O., TD. Taipei Office Macronix, Int'l Co., Ltd. 19F, 4, Min-Chuan E. Road, Sec. 3, Taipei, Taiwan, R.O.C. Tel: +886-2-2509-3300 Fax: +886-2-2509-2200 Macronix Europe N ...