mx25l12845e Macronix International Co., mx25l12845e Datasheet
mx25l12845e
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mx25l12845e Summary of contents
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... HIGH PERFORMANCE SERIAL FLASH SPECIFICATION P/N: PM1428 MX25L12845E PRELIMINARY 1 MX25L12845E REV. 0.06, MAR. 05, 2009 ...
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... Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4), (REMS4D) ............................. 28 Table 8. ID Definitions ............................................................................................................................................ 29 (24) Enter Secured OTP (ENSO) ........................................................................................................................... 29 (26) Read Security Register (RDSCUR) ................................................................................................................. 29 (25) Exit Secured OTP (EXSO) .............................................................................................................................. 30 Security Register Definition .................................................................................................................................... 30 (27) Write Security Register (WRSCUR) ................................................................................................................ 30 P/N: PM1428 MX25L12845E Contents 2 REV. 0.06, MAR. 05, 2009 ...
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... Figure 33. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB Figure 34. Release from Deep Power-down (RDP) Sequence (Command AB) .................................................... 56 Figure 35. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command CF) .... 56 Figure 36. READ ARRAY SEQUENCE (Parallel) .................................................................................................. 57 Figure 37. AUTO PAGE PROGRAM TIMING SEQUENCE (Parallel) ................................................................... 58 P/N: PM1428 MX25L12845E 3 REV. 0.06, MAR. 05, 2009 ...
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... Figure 43. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98) ............................................. 62 Figure 44. Power-up Timing .................................................................................................................................... 63 Table 11. Power-Up Timing and VWI Threshold ..................................................................................................... 63 INITIAL DELIVERY STATE ..................................................................................................................................... 63 RECOMMENDED OPERATING CONDITIONS ......................................................................................................... 64 ERASE AND PROGRAMMING PERFORMANCE .................................................................................................... 65 LATCH-UP CHARACTERISTICS .............................................................................................................................. 65 ORDERING INFORMATION ...................................................................................................................................... 66 PART NAME DESCRIPTION ..................................................................................................................................... 67 PACKAGE INFORMATION ........................................................................................................................................ 68 REVISION HISTORY ................................................................................................................................................. 69 P/N: PM1428 MX25L12845E 4 REV. 0.06, MAR. 05, 2009 ...
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... Low active erase current: 25mA (max.) - Low standby current: 100uA (max.) - Deep power down current: 40uA (max.) • Typical 100,000 erase/program cycles SOFTWARE FEATURES • Input Data Format - 1-byte Command code P/N: PM1428 MX25L12845E TM (SERIAL MULTI I/O) FLASH MEMORY 5 PRELIMINARY REV. 0.06, MAR. 05, 2009 ...
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... WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O mode • NC/SIO3 - NC pin or serial data Input/Output for 4 x I/O mode • PO0~PO6 - For parallel mode data • PACKAGE - 16-pin SOP (300mil) - All Pb-free devices are RoHS Compliant P/N: PM1428 MX25L12845E 6 REV. 0.06, MAR. 05, 2009 ...
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... MX25L12845E is 134,217,728 bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When two or four I/O mode, the structure becomes 67,108,864 bits 33,554,432 bits x 4. The MX25L12845E features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO) ...
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... NC/SIO3 VCC GND PO0~PO6 Parallel data output/input (PO0~PO6 can NC 8 MX25L12845E DESCRIPTION Chip Select Serial Data Input (for 1xI/O)/ Serial Data Input & Output (for 2xI/O or 4xI/O mode) Serial Data Output (for 1xI/O)/Serial Data Input & Output (for 2xI/O or 4xI/O ...
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... BLOCK DIAGRAM SI/SIO0 CS# WP#/SIO2 NC/SIO3 SCLK SO/SIO1 P/N: PM1428 MX25L12845E Address Generator Data Register SRAM Buffer Mode State Logic Machine Generator Clock Generator 9 Memory Array Page Buffer Y-Decoder Sense Amplifier HV Output Buffer REV. 0.06, MAR. 05, 2009 ...
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... The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit. If the system goes into four I/O mode, the feature of HPM will be disabled. - MX25L12845E provide individual block (or sector) write protect & unprotect. User may enter the mode with WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for individual block (or sector) unprotect ...
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... Upper sixteenth (sixteen blocks: 240 to 255) Upper 32nd (eight blocks: 248 to 255) Upper 64th (four blocks: 252 to 255) Upper 128th (two blocks: 254 and 255) None Size Standard Factory Lock ESN (electrical serial number) N/A 11 MX25L12845E Customer Lock Determined by customer REV. 0.06, MAR. 05, 2009 ...
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... MX25L12845E FFFFFFh individual 16 sectors FF8FFFh lock/unlock unit:4K-byte FF7FFFh FF0FFFh FEFFFFh FE8FFFh FE7FFFh FE0FFFh FDFFFFh FD8FFFh FD7FFFh FD0FFFh 02FFFFh 028FFFh 027FFFh 020FFFh 01FFFFh 018FFFh 017FFFh 010FFFh 00FFFFh ...
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... Figure 1-2. Serial Modes Supported (for Double Transfer Rate serial read mode) CPOL CPHA SCLK (Serial mode (Serial mode 3) SCLK SI SO P/N: PM1428 MX25L12845E shift in shift out MSB data data in in MSB 13 MSB data data out out REV. 0.06, MAR. 05, 2009 ...
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... AD3 continously enters release program deep from deep whole chip, power power the address is down down automatically mode mode increase 14 MX25L12845E FASTDTRD 2DTRD 4DTRD (fast DT (Dual I/O (Quad I/O read) DT Read) DT Read) 0D (hex) BD (hex) ED (hex) ADD(2) & ADD(4) & ADD1 Dummy(2) Dummy(4) ADD(1) & ...
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... MX25L12845E ESRY DSRY ENPLM (write (enable (disable (Enter Parallel output RY/ output RY/ Mode) BY#) BY#) 70 (hex) 80 (hex) 55 (hex) to enable to disable 8xI/O ...
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... SO → to end RDID operation can use CS# to high at any time during data out. (see Figure 13 and Figure 14 for parallel mode) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy- cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. P/N: PM1428 MX25L12845E 16 REV. 0.06, MAR. 05, 2009 ...
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... Quad 1=status Enable register write (note 1) 0=not Quad disable Enable Non-volatile Non-volatile Non-volatile bit bit bit Note 1: see the Table 2 "Protected Area Size" in page 11. P/N: PM1428 MX25L12845E bit4 bit3 bit2 BP2 BP1 BP0 (level of (level of (level of protected protected protected block) block) block) ...
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... If the system goes into four I/O mode, the feature of HPM will be disabled. P/N: PM1428 WP# and SRWD bit status WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 WP#=0, SRWD bit=1 changed 18 MX25L12845E Memory The protected area cannot be program or erase. The protected area cannot be program or erase. REV. 0.06, MAR. 05, 2009 ...
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... CS# to high at any time during data out (see Figure 20 for 2 x I/O Read Mode Timing Waveform). While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM1428 MX25L12845E 19 REV. 0.06, MAR. 05, 2009 ...
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... SI (2-bit per clock) → 6-dummy clocks (default → data out on SO (2-bit per clock) → to end FASTDTRD operation can use CS# to high at any time during data out. (see Figure 19) While Program/Erase/Write Status Register cycle is in progress, FASTDTRD instruction is rejected without any im- pact on the Program/Erase/Write Status Register current cycle. P/N: PM1428 MX25L12845E 20 REV. 0.06, MAR. 05, 2009 ...
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... CS# goes low (eliminate 4 Read instruction) → 24-bit random access address (see Figure 25 for Double Transfer Rate read enhance performance mode timing waveform). While Program/Erase/Write Status Register cycle is in progress, 4DTRD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM1428 MX25L12845E 21 REV. 0.06, MAR. 05, 2009 ...
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... Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3~0 (WPSEL= individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit still be reset. P/N: PM1428 MX25L12845E 22 REV. 0.06, MAR. 05, 2009 ...
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... The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high. (see Figure 27) P/N: PM1428 MX25L12845E If more than 256 bytes are sent to the device, the data of the 23 REV. 0.06, MAR. 05, 2009 ...
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... RDSR command WIP=0? Yes Read array data (same address of PGM/ERS) Verify OK? Yes Program/erase successfully Program/erase another block? No Program/erase completed P/N: PM1428 MX25L12845E Program/erase fail CLSR(30h) command Yes * * Issue RDSR to check BP[3:0 WPSEL=1, issue RDBLOCK to check the block status. 24 REV. 0.06, MAR. 05, 2009 ...
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... Write program data/address (Write erase address) RDSR command WIP=0? Yes RDSCUR command REGPFAIL/REGEFAIL=1? No Program/erase successfully Program/erase another block? No Program/erase completed P/N: PM1428 MX25L12845E No No Yes Program/erase fail CLSR(30h) command Yes * Issue RDSR to check BP[3:0 WPSEL=1, issue RDBLOCK to check the block status. 25 REV. 0.06, MAR. 05, 2009 ...
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... Only effective for Read Array for normal read(not FAST_READ), Read ID, Page Program, RES and REMS write data period. b. For normal write command (by SI), No effect c. Under parallel mode, the fastest access clock freq. will be changed to 6MHz(SCLK pin clock freq.) d. For parallel mode, the tV will be changed to 70ns. P/N: PM1428 MX25L12845E 26 REV. 0.06, MAR. 05, 2009 ...
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... The Device ID values are listed in table of ID Definitions. If the one-byte address is initially set to 01h, then the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. P/N: PM1428 MX25L12845E 27 REV. 0.06, MAR. 05, 2009 ...
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... Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus- tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be update any more. While 4K-bit Secured OTP mode, array access is not allowed. P/N: PM1428 MX25L12845E memory type C2 20 ...
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... OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. P/N: PM1428 MX25L12845E bit4 bit3 bit2 ...
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... RDSCUR(2Bh) command WPSEL=1? WPSEL disable, block protected by BP[3:0] WPSEL(68h) command RDSR command WIP=0? RDSCUR(2Bh) command WPSEL=1? WPSEL set successfully WPSEL enable. Block protected by individual lock (SBLK, SBULK, … etc). P/N: PM1428 start Yes No No Yes No Yes WPSEL set fail 30 MX25L12845E REV. 0.06, MAR. 05, 2009 ...
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... WREN command SBLK command ( 36h + 24bit address ) RDSR command WIP=0? RDBLOCK command ( 3Ch + 24bit address ) Data = FFh ? Block lock successfully Lock another block? Block lock completed P/N: PM1428 No WPSEL command Yes No Yes No Yes Block lock fail Yes No 31 MX25L12845E REV. 0.06, MAR. 05, 2009 ...
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... Block Unlock Flow start RDSCUR(2Bh) command WPSEL=1? WREN command SBULK command ( 39h + 24bit address ) RDSR command WIP=0? Unlock another block? Unlock block completed? P/N: PM1428 No WPSEL command Yes No Yes Yes 32 MX25L12845E REV. 0.06, MAR. 05, 2009 ...
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... The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction. The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction → CS# goes high. (see Figure 43) The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. P/N: PM1428 MX25L12845E 33 REV. 0.06, MAR. 05, 2009 ...
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... The sequence of issuing DSRY instruction is: CS# goes low → send DSRY instruction code → CS# goes high. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. (34) Enter CFI mode (ENCFI) TBD P/N: PM1428 MX25L12845E 34 REV. 0.06, MAR. 05, 2009 ...
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... The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the figure of "Power-up Timing". Note stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) P/N: PM1428 MX25L12845E 35 REV. 0.06, MAR. 05, 2009 ...
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... During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 2, 3. Figure 2. Maximum Negative Overshoot Waveform 20ns 20ns Vss Vss-2.0V 20ns CAPACITANCE TA = 25° 1.0 MHz SYMBOL PARAMETER CIN Input Capacitance COUT Output Capacitance P/N: PM1428 MX25L12845E Industrial grade Figure 3. Maximum Positive Overshoot Waveform Vcc + 2.0V Vcc 20ns MIN. TYP MAX. UNIT ...
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... DEVICE UNDER TEST CL=30pF Including jig capacitance (CL=15pF Including jig capacitance for 104MHz, 70MHz@2xI/O and 70MHz@4xI/O) P/N: PM1428 Output timing referance level 0.7VCC AC Measurement Level 0.8V Note: Input pulse rise and fall time are <5ns 2.7K ohm CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT 37 MX25L12845E 0.5VCC +3.3V REV. 0.06, MAR. 05, 2009 ...
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... V 0.7VCC VCC+0.4 V 0.4 V VCC-0 MX25L12845E VCC = VCC Max, VIN = VCC or GND VCC = VCC Max, VIN = VCC or GND VIN = VCC or GND, CS# = VCC VIN = VCC or GND, CS# = VCC f=104MHz, fQ=75MHz (2 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open f=66MHz, fT=75MHz (4 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open f=33MHz, SCLK=0 ...
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... VCC=2.7V~3.6V tCLQV2 tV2 Clock Low to Output Valid (DTR mode) VCC=2.7V~3.6V, Loading: 15pF tCLQX tHO Output Hold Time tWHSL(4) Write Protect Setup Time tSHWL(4) Write Protect Hold Time P/N: PM1428 MX25L12845E Serial Parallel Serial Parallel Serial Parallel Serial Parallel Serial Parallel Serial Parallel ...
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... Value guaranteed by characterization, not 100% tested in production. 3. tSHSL=15ns from read instruction, tSHSL=50ns from Write/Erase/Program instruction. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set Test condition is shown as Figure Only valid in output phase delay configuration "00". P/N: PM1428 MX25L12845E Min. Typ 1 ...
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... Timing Analysis Figure 6. Serial Input Timing CS# tCHSL SCLK tDVCH SI SO Figure 7. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1428 tSLCH tCHSH tCHDX tCLCH MSB High-Z tCH tCLQV 41 MX25L12845E tSHSL tSHCH tCHCL LSB tCL tSHQZ LSB tQLQH tQHQL REV. 0.06, MAR. 05, 2009 ...
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... SI SO Figure 9. Serial Output Timing for Double Transfer Rate Mode CS# SCLK tCLQV2 tCLQV2 tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1428 tSLCH tCHSH tDVCH tCHDX tCLCH MSB High-Z tCH tCLQV2 tQLQH tQHQL 42 MX25L12845E tSHSL tSHCH tCHCL LSB tCL tSHQZ LSB REV. 0.06, MAR. 05, 2009 ...
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... Figure 11. Write Enable (WREN) Sequence (Command 06) CS# SCLK SI SO Figure 12. Write Disable (WRDI) Sequence (Command 04) CS# SCLK SI SO P/N: PM1428 Command 06 High Command 04 High-Z 43 MX25L12845E tSHWL REV. 0.06, MAR. 05, 2009 ...
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... Type) and Device ID 2'nd byte (Memory Density). P/N: PM1428 Manufacturer Identification MSB MSB Manufacturer Identification Device Identification 44 MX25L12845E Device Identification REV. 0.06, MAR. 05, 2009 ...
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... Status Register Out MSB MSB command Status Register MSB High-Z 45 MX25L12845E Status Register Out REV. 0.06, MAR. 05, 2009 ...
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... BIT ADDRESS DATA OUT MSB 46 MX25L12845E Data Out 1 Data Out DATA OUT MSB MSB ...
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... Address Cycle cycle address dummy bit22, bit20, bit18...bit0 address dummy bit23, bit21, bit19...bit1 47 MX25L12845E Data output Data Output data bit6, bit4, bit2...bit0, bit6, bit4.... ...
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... Indicator (Note1, 2) address P4 P0 bit20, bit16..bit0 address P5 P1 bit21, bit17..bit1 address P6 P2 bit22, bit18..bit2 address P7 P3 bit23, bit19..bit3 48 MX25L12845E Data output n Data Output data bit4, bit0, bit4.... data bit5 bit1, bit5.... data bit6 bit2, bit6.... ...
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... P4 P0 bit4, bit0, bit4.... data P5 P1 bit5 bit1, bit5.... data P6 P2 bit6 bit2, bit6.... data P7 P3 bit7 bit3, bit7.... 49 MX25L12845E n Data Output data bit4, bit0, bit4.... data bit5 bit1, bit5.... data bit6 bit2, bit6.... data bit7 bit3, bit7.... REV. 0.06, MAR. 05, 2009 ...
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... Performance Enhance Indicator (Note1, MX25L12845E Data output . . . . . . ...
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... • • • • • • • • • • • • • • • • 51 MX25L12845E Data output • • • ...
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... Address cycles Byte MX25L12845E Data Byte Data Byte 256 Data Data Data Byte 2 Byte 3 Byte ...
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... Byte 0, Byte1 status ( Command 24 Bit Address MSB Command 24 Bit Address MSB 53 MX25L12845E data in 04 (hex) 05 (hex REV. 0.06, MAR. 05, 2009 ...
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... DP Command B9 Stand-by Mode Dummy Bytes MSB Electronic Signature Out MSB Deep Power-down Mode 54 MX25L12845E Deep Power-down Mode RES2 Stand-by Mode REV. 0.06, MAR. 05, 2009 ...
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... Dummy Bytes ADD ( Manufacturer MSB 55 MX25L12845E Stand-by Mode 47 Device MSB MSB REV. 0.06, MAR. 05, 2009 ...
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... Byte 2 Byte 2 Byte 1 Byte 1 …………. …………. 56 MX25L12845E Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 2nd byte (AD1) 2nd byte (AD1) ...
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... Byte 1 Byte 1 Byte 2 Byte 2 …………. …………. 57 MX25L12845E Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 2nd byte (AD1) 2nd byte (AD1) ...
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... To exit parallel mode, it requires a (45h) command or power-off/on sequence. P/N: PM1428 Dummy Bytes Electronic Signature Out Byte Output Deep Power-down Mode 58 MX25L12845E RES2 Stand-by Mode REV. 0.06, MAR. 05, 2009 ...
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... To read ID in parallel mode, which requires a parallel mode command (55h) before the read ID command. To exit Parallel mode, it requires a (45h) command or power-off/on sequence. P/N: PM1428 Dummy Bytes Manufacturer ID Device ID 59 MX25L12845E 47 REV. 0.06, MAR. 05, 2009 ...
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... Command 24 Bit Address 23 22 36/39 MSB Address Bytes MSB Block Protection Lock status out MSB 60 MX25L12845E REV. 0.06, MAR. 05, 2009 ...
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... Figure 43. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98) CS# SCLK SI P/N: PM1428 MX25L12845E Command 7E/98 61 REV. 0.06, MAR. 05, 2009 ...
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... The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1428 Chip Selection is Not Allowed tVSL 62 MX25L12845E Device is fully accessible time Min. Max. Unit ...
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... For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1428 tSLCH tDVCH tCHDX MSB IN High Impedance Figure A. AC Timing at Device Power-Up Notes 1 63 MX25L12845E tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN Min. Max. Unit 20 500000 us/V REV ...
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... LATCH-UP CHARACTERISTICS Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1428 MX25L12845E Min. TYP. (1) Max. (2) 40 100 90 300 0 ...
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... ORDERING INFORMATION CLOCK PART NO. (MHz) MX25L12845EMI-10G 104 P/N: PM1428 OPERATING STANDBY CURRENT CURRENT TEMPERATURE MAX. (mA) MAX. (uA) 45 100 -40°C~85°C 65 MX25L12845E PACKAGE Remark 16-SOP Pb-free REV. 0.06, MAR. 05, 2009 ...
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... PART NAME DESCRIPTION P/N: PM1428 12845E OPTION: G: Pb-free SPEED: 10: 104MHz TEMPERATURE RANGE: I: Industrial (-40° 85° C) PACKAGE: M: 300mil 16-SOP DENSITY & MODE: 12845E: 128Mb standard type TYPE DEVICE: 25: Serial Flash 66 MX25L12845E REV. 0.06, MAR. 05, 2009 ...
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... PACKAGE INFORMATION P/N: PM1428 MX25L12845E 67 REV. 0.06, MAR. 05, 2009 ...
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... Added trademark MXSMIO 11. Modified Figure 4. 12. Revised the tV of parallel mode 13. Revised RDSLOCK into RDBLOCK and added BE32K and 4PP 14. Added CFh 15. Changed "ADVANCED INFORMATION" into "Preliminary" P/N: PM1428 MX25L12845E TM (Serial Multi I/O) flash memory 68 Page Date P5,33~35 JAN/25/2008 ...
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... Fax: +86-512-62586799 Macronix (Hong Kong) Co., Limited, Shenzhen Office Room 1401 & 1404, Blcok A, TianAN Hi-Tech PLAZA Tower, Che Gong Miao, FutianDistrict, Shenzhen PRC 518040 Tel: +86-755-83433579 Fax: +86-755-83438078 http : //www.macronix.com MX25L12845E C L O., TD. Macronix Offices : Japan Macronix Asia Limited. NKF Bldg. 5F, 1-2 Higashida-cho, Kawasaki-ku Kawasaki-shi, Kanagawa Pref ...