mx25l3205azmi-20g Macronix International Co., mx25l3205azmi-20g Datasheet
mx25l3205azmi-20g
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mx25l3205azmi-20g Summary of contents
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FEATURES GENERAL • Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3 • 33,554,432 x 1 bit structure • 64 Equal Sectors with 64K byte each - Any sector can be erased • Single Power Supply Operation - ...
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GENERAL DESCRIPTION The MX25L3205A is a CMOS 33,554,432 bit serial TM eLiteFlash Memory, which is configured as 4,194,304 x 8 internally. The MX25L3205A features a serial peripheral interface and software protocol allowing operation on a simple 3- wire bus. The ...
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BLOCK DIAGRAM Address Generator SI CS#, ACC, WP#,HOLD# SCLK P/N: PM1243 Memory Array Data Register Y-Decoder SRAM Buffer Mode State HV Logic Machine Generator Clock Generator 3 MX25L3205A Output Sense Buffer Amplifier SO REV. 1.2, NOV. 06, 2006 ...
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DATA PROTECTION The MX25L3205A are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. ...
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Table 1. Protected Area Sizes Status bit BP2 BP1 BP0 Note: 1. The device is ready ...
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HOLD FEATURE HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select(CS#) keeping ...
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Table 2. COMMAND DEFINITION COMMAND WREN WRDI (byte) (write (write Enable) disable) 1st 06 Hex 04 Hex 2nd 3rd 4th 5th Action sets the reset the output the (WEL) (WEL) write write enable enable latch bit latch bit COMMAND SE ...
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Sector Address Range 63 3F0000h 62 3E0000h 61 3D0000h 60 3C0000h 59 3B0000h 58 3A0000h 57 390000h 56 380000h 55 370000h 54 360000h 53 350000h 52 340000h 51 330000h 50 320000h 49 310000h 48 300000h 47 2F0000h 46 2E0000h 45 ...
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DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby ...
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COMMAND DESCRIPTION (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, CE, and WRSR, which are intended to change the device content, should be set every ...
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Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously recommended to check the Write in ...
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Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ...
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Note: If SRWD bit=1 but WP# is low impossible to write the Status Register even if the WEL bit has previously been set rejected to write the Status Register and not be executed. Hardware Protected Mode ...
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Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector ...
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Enter 4Kbit Mode (EN4K) and Exit 4Kbit Mode (EX4K) Enter and Exit 4kbit mode (EN4K & EX4K) (see Figure 27 & 28) EN4K and EX4K will not be executed when the chip is in busy state. Enter 4kbit mode ...
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SCLK while CS low. If the device was not previously in Deep Power- down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down ...
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POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down ...
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature - for Industrial grade for Commercial grade Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential Figure 4.Maximum Negative ...
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Figure 6. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing referance level 0.8VCC 0.2VCC Figure 7. OUTPUT LOADING DEVICE UNDER TEST P/N: PM1243 MX25L3205A Output timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time ...
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Table 5. DC CHARACTERISTICS (Temperature = - for Industrial grade, Temperature = SYMBOL PARAMETER NOTES ILI Input Load Current ILO Output Leakage Current ISB1 VCC Standby Current ISB2 Deep Power-down Current ICC1 VCC Read ICC2 VCC ...
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Table 6. AC CHARACTERISTICS (Temperature = - for Industrial grade, Temperature = Symbol Alt. Parameter fSCLK fC Clock Frequency for the following instructions: FAST_READ, PP, SE, BE, DP, RES,REMS, RDP WREN, WRDI, RDID, RDSR, WRSR, EN4K, ...
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Table 7. Power-Up Timing and VWI Threshold Symbol Parameter tVSL(1) VCC(min low tPUW(1) Time delay to Write instruction VWI(1) Write Inhibit Voltage Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the ...
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Figure 8. Serial Input Timing CS# tCHSL SCLK tDVCH SI High-Z SO Figure 9. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1243 MX25L3205A tSLCH tCHSH tCHDX tCLCH MSB LSB tCH tCLQV tCL tQLQH tQHQL 23 ...
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Figure 10. Hold Timing CS# SCLK SO HOLD "don't care" during HOLD operation. Figure 11. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tWHSL CS SCLK SI High-Z SO P/N: PM1243 tHLCH ...
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Figure 12. Write Enable (WREN) Sequence (Command 06) CS# SCLK SI SO Figure 13. Write Disable (WRDI) Sequence (Command 04) CS# SCLK SI SO Figure 14. Read Identification (RDID) Sequence (Command 9F) CS SCLK Command SI ...
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Figure 15. Read Status Register (RDSR) Sequence (Command 05) CS SCLK command SI High-Z SO Notes: In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip ...
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Figure 18. Read Data Bytes at Higher Speed (FAST_READ) Sequence (Command 0B) CS SCLK Command SI 0B High SCLK Dummy Byte Notes: In READ mode, FAST_READ ...
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Figure 19. Page Program (PP) Instruction Sequence CS SCLK Command SI CS SCLK Data Byte MSB Figure 20. Sector Erase ...
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Figure 21. Chip Erase (CE) Sequence (Command 60 or C7) CS# SCLK SI Note: CE command is 60(hex) or C7(hex). Figure 22. Deep Power-down (DP) Sequence (Command B9) CS SCLK SI Figure 23. Release from Deep Power-down and ...
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Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB) CS SCLK SI High-Z SO Figure 25. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90) CS SCLK Command SI 90 High-Z SO ...
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Figure 26. Power-up Timing (max) Program, Erase and Write Commands are Ignored Chip Selection is Not Allowed V CC (min) Reset State of the Flash V WI P/N: PM1243 MX25L3205A tVSL Read Command is Device is ...
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Figure 27. Enter 4Kbit Mode (EN4K) Sequence (Command A5) CS# SCLK SI SO Figure 28. Exit 4Kbit Mode (EX4K) Sequence (Command B5) CS# SCLK SI SO Note: Enter and Exit 4kbit mode (EN4K & EX4K) EN4K and EX4K will not ...
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Figure 29. READ ARRAY SEQUENCE (Parallel) NOTES: 1. 1st Byte='03h' 2. 2nd Byte=Address 1(AD1), AD23=BIT7, AD22=BIT6, AD21=BIT5, AD20=BIT4,....AD16=BIT0. 3. 3rd Byte=Address 2(AD2), AD15=BIT7, AD14=BIT6, AD13=BIT5, AD12=BIT4,....AD8=BIT0. 4. 4th Byte=Address 3(AD3), AD7=BIT7, AD6=BIT6, ....AD0=BIT0. 5. From Byte 5, SO Would Output ...
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Figure 30. AUTO PAGE PROGRAM TIMING SEQUENCE (Parallel) NOTES: 1. 1st Byte='02h' 2. 2nd Byte=Address 1(AD1), AD23=BIT7, AD22=BIT6, AD21=BIT5, AD20=BIT4,....AD16=BIT0. 3. 3rd Byte=Address 2(AD2), AD15=BIT7, AD14=BIT6, AD13=BIT5, AD12=BIT4,....AD8=BIT0. 4. 4th Byte=Address 3(AD3), AD7=BIT7, AD6=BIT6, ....AD0=BIT0. 5. 5th byte: 1st write ...
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Figure 31. Read Identification (RDID) Sequence (Parallel) CS SCLK Command SI High-Z PO7~0 NOTES: 1. Under parallel mode, the fastest access clock freg. will be changed to 1.2MHz(SCLK pin clock freg.) To read identification in parallel mode, ...
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Figure 32. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Parallel) CS SCLK Command SI AB High-Z PO7~0 NOTES: 1. Under parallel mode, the fastest access clock freg. will be changed to ...
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Figure 33. READ STATUS REGISTER TIMING SEQUENCE (Parallel) NOTES: 1. 1st Byte='05h' 2. BIT7 status register write disable signal. BIT7=1, means SR write disable. 3. BIT6=0 ==> Program/erase is correct. 4. BIT4 defines the level of protected block. ...
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Figure 34. Read Electronic Manufacturer & Device ID (REMS) Sequence (Parallel) CS SCLK Command SI High-Z PO7~0 CS# SCLK PO7~0 NOTES: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will ...
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RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) ...
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ERASE AND PROGRAMMING PERFORMANCE PARAMETER Chip Erase Time Chip Erase Time (with ACC=12V) Sector erase Time Sector erase Time (with ACC=12V) Additional 4Kb Erase Time Page Programming Time Page Programming Time (with ACC=12V) Erase/Program Main Array Cycle Additional 4Kb Note: ...
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... ORDERING INFORMATION PART NO. ACCESS TIME(ns) MX25L3205AMC-20 20 MX25L3205AMC-20G 20 MX25L3205AMI-20 20 MX25L3205AMI-20G 20 MX25L3205AZMC-20G 20 MX25L3205AZMI-20G 20 P/N: PM1243 MX25L3205A OPERATING STANDBY Temperature PACKAGE CURRENT(mA) CURRENT(uA Remark 0~70 C 16-SOP 0~70 C 16-SOP Pb-free -40~85 C 16-SOP -40~85 C 16-SOP Pb-free 0~70 C 8-SON Pb-free -40~85 C 8-SON Pb-free REV. 1.2, NOV. 06, 2006 ...
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PART NAME DESCRIPTION 3205A P/N: PM1243 MX25L3205A OPTION: G: Pb-free blank: normal SPEED: 20: 50MHz, for SPI TEMPERATURE RANGE: C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: M: 300mil 16-SOP ...
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PACKAGE INFORMATION P/N: PM1243 MX25L3205A 43 REV. 1.2, NOV. 06, 2006 ...
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P/N: PM1243 MX25L3205A 44 REV. 1.2, NOV. 06, 2006 ...
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REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" title 1.1 1. Format change 1.2 1. Added statement P/N: PM1243 MX25L3205A Page P1 All P46 45 Date OCT/13/2005 JUN/08/2006 NOV/06/2006 REV. 1.2, NOV. 06, 2006 ...
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... Macronix's products in the prohibited applications ACRONIX NTERNATIONAL Headquarters Macronix America, Inc. Macronix Japan Cayman Islands Ltd. Macronix (Hong Kong) Co., Limited. http : //www.macronix.com MX25L3205A C L O., TD. Taipei Office Macronix Europe N.V. Singapore Office MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 46 ...