mx25l3237d Macronix International Co., mx25l3237d Datasheet
mx25l3237d
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mx25l3237d Summary of contents
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... P/N: PM1393 MX25L3237D DATASHEET 1 MX25L3237D REV. 0.02, JUN. 13, 2008 ...
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... I/O Read Mode (2READ) ....................................................................................................................... 19 ( I/O Read Mode (4READ) ....................................................................................................................... 20 (10) Sector Erase (SE) ..................................................................................................................................... 20 (11) Block Erase (BE) ...................................................................................................................................... 20 (12) Chip Erase (CE) ........................................................................................................................................ 21 (13) Page Program (PP) ................................................................................................................................... 21 (14 I/O Page Program (4PP) ...................................................................................................................... 22 (15) Continuously program mode (CP mode) ..................................................................................................... 22 (16) Deep Power-down (DP) ............................................................................................................................. 22 P/N: PM1393 MX25L3237D Contents 2 REV. 0.02, JUN. 13, 2008 ...
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... Figure 20 I/O Page Program (4PP) Sequence (Command 38) ................................................................... 38 Figure 21. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD) ....................... 39 Figure 22. Sector Erase (SE) Sequence (Command 20) .................................................................................. 39 Figure 23. Block Erase (BE) Sequence (Command D8) ................................................................................... 39 Figure 24. Chip Erase (CE) Sequence (Command 60 or C7) ............................................................................ 40 P/N: PM1393 MX25L3237D 3 REV. 0.02, JUN. 13, 2008 ...
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... Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command DF) ............. 41 Figure 29. Power-up Timing .............................................................................................................................. 42 Table 12. Power-Up Timing and VWI Threshold ................................................................................................. 42 INITIAL DELIVERY STATE .............................................................................................................................. 42 RECOMMENDED OPERATING CONDITIONS .......................................................................................................... 43 ERASE AND PROGRAMMING PERFORMANCE ...................................................................................................... 44 LATCH-UP CHARACTERISTICS ............................................................................................................................... 44 ORDERING INFORMATION ...................................................................................................................................... 45 PART NAME DESCRIPTION ..................................................................................................................................... 46 PACKAGE INFORMATION ......................................................................................................................................... 47 REVISION HISTORY ................................................................................................................................................. 49 P/N: PM1393 MX25L3237D 4 REV. 0.02, JUN. 13, 2008 ...
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... Input Data Format - 1-byte Command code • Advanced Security Features - Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions P/N: PM1393 ADVANCED INFORMATION MX25L3237D 32M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH 5 REV. 0.02, JUN. 13, 2008 ...
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... WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O read mode • NC/SIO3 - NC pin or serial data Input/Output for 4 x I/O read mode • PACKAGE - 16-pin SOP (300mil) - 8-land WSON (6 x 5mm) - All Pb-free devices are RoHS Compliant P/N: PM1393 MX25L3237D 6 REV. 0.02, JUN. 13, 2008 ...
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... The MX25L3237D are 32,554,432 bit serial Flash memory, which is configured as 4,194,304 x 8 internally. When two or four I/O read mode, the structure becomes 16,777,216 bits 8,388,608 bits x 4. The MX25L3237D feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO) ...
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... WP# 3 SCLK 6 4 SI/SIO0 GND 4 * Note: 8 Land WSON does not support 4 I/O function. P/N: PM1393 MX25L3237D PIN DESCRIPTION SYMBOL DESCRIPTION CS# Chip Select SI/SIO0 Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/O read mode) SO/SIO1 Serial Data Output (for 1 x I/O)/ Serial Data Input & ...
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... BLOCK DIAGRAM SI/SIO0 CS# WP#/SIO2 NC/SIO3 SCLK SO/SIO1 P/N: PM1393 Address Generator Memory Array Page Buffer Data Register SRAM Buffer Mode State Logic Machine Generator Clock Generator 9 MX25L3237D Y-Decoder Sense Amplifier HV Output Buffer REV. 0.02, JUN. 13, 2008 ...
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... DATA PROTECTION The MX25L3237D is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences ...
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... Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition Address range Size xxx000~xxx00F 128-bit xxx010~xxx1FF 3968-bit P/N: PM1393 Protect Level 32Mb Standard Factory Lock ESN (electrical serial number) N/A 11 MX25L3237D Customer Lock Determined by customer REV. 0.02, JUN. 13, 2008 ...
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... MX25L3237D Address Range Sector 767 2FF000h 2FFFFFh . . . . . . . . . 752 2F0000h 2F0FFFh 751 2EF000h 2EFFFFh . . . . . . . . . 736 2E0000h 2E0FFFh 735 2DF000h 2DFFFFh . . . . . . . . . 720 2D0000h 2D0FFFh 719 2CF000h 2CFFFFh ...
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... MX25L3237D Address Range 255 0FF000h 0FFFFFh . . . . . . . . . 240 0F0000h 0F0FFFh 239 0EF000h 0EFFFFh . . . . . . . . . 224 0E0000h 0E0FFFh 223 0DF000h 0DFFFFh . . . . . . . . . 208 0D0000h 0D0FFFh 207 0CF000h 0CFFFFh . . ...
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... CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1393 shift in MSB 14 MX25L3237D shift out MSB REV. 0.02, JUN. 13, 2008 ...
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... COMMAND DESCRIPTION Table 5. Command Set P/N: PM1393 MX25L3237D 15 REV. 0.02, JUN. 13, 2008 ...
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... RDID operation can use CS# to high at any time during data out. (see Figure 11.) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. P/N: PM1393 MX25L3237D 16 REV. 0.02, JUN. 13, 2008 ...
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... Enable 1= status (note1) register write 0=not Quad Enable disable Non- volatile bit Non- volatile bit Non- volatile bit Note 1: see the table 2 "Protected Area Size" in page 11. P/N: PM1393 MX25L3237D bit4 bit3 bit2 BP2 BP1 BP0 (level of (level of (level of protected block) protected block) ...
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... If SRWD bit=1 but WP#/SIO2 is low impossible to write the Status Register even if the WEL bit has previously been set rejected to write the Status Register and not be executed. P/N: PM1393 MX25L3237D WP# and SRWD bit status WP#=1 and SRWD bit=0, or The protected area cannot WP#=0 and SRWD bit= program or erase ...
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... CS# to high at any time during data out (see Figure 16 for 2 x I/O Read Mode Timing Waveform). While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM1393 MX25L3237D sending 2READ instruction data out interleave on SIO1 & SIO0 19 ...
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... The sequence of issuing BE instruction is: CS# goes low -> sending BE instruction code-> 3-byte address on SI -> CS# goes high. (see Figure 23) P/N: PM1393 MX25L3237D sending 4READ instruction data out interleave on SIO3, SIO2, SIO1 & SIO0 performance enhance toggling bit P[7:0] ...
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... Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. P/N: PM1393 MX25L3237D 21 REV. 0.02, JUN. 13, 2008 ...
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... CP mode. (16) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the P/N: PM1393 MX25L3237D 22 REV. 0.02, JUN. 13, 2008 ...
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... Table of ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. P/N: PM1393 MX25L3237D 23 REV. 0.02, JUN. 13, 2008 ...
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... While 4K-bit secured OTP mode, array access is not allowed. Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP mode, "0" indicates not in CP mode; "1" indicates in CP mode. P/N: PM1393 MX25L3237D MX25L3237D Memory type Memory Density 5E 16 ...
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... Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low-> sending WRSCUR instruction -> CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. P/N: PM1393 MX25L3237D bit4 bit3 bit2 Continuously ...
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... At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress. P/N: PM1393 MX25L3237D 26 REV. 0.02, JUN. 13, 2008 ...
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... All input and output pins may overshoot to VI/O+0.5V while VI/O+0.5V is smaller than or equal to 4.6V. Figure 2.Maximum Negative Overshoot Waveform 20ns 0V -0.5V CAPACITANCE TA = 25° 1.0 MHz SYMBOL PARAMETER CIN Input Capacitance COUT Output Capacitance P/N: PM1393 MX25L3237D VALUE - for Industrial grade - 125 C -0.5V to 4.6V -0.5V to 4.6V -0.5V to 4.6V Figure 3. Maximum Positive Overshoot Waveform 4.6V 3.6V MIN. TYP MAX. ...
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... Figure 5. OUTPUT LOADING P/N: PM1393 Output timing referance level AC Measurement Level Note: Input pulse rise and fall time are <5ns VI/O R1 DEVICE UNDER OUT TEST CL R2 CL=30pF Including jig capacitance (CL=15pF Including jig capacitance for x1/x2/x4 I/O Fast Read) R1=R2=25K ohm 28 MX25L3237D 0.5VI/O REV. 0.02, JUN. 13, 2008 ...
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... MX25L3237D TEST CONDITIONS VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VIN = VCC or GND CS# = VCC VIN = VCC or GND CS# = VCC f=86MHz fQ=75MHz (4 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open f=66MHz fT=75MHz (2 x I/O read) SCLK=0 ...
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... VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage P/N: PM1393 VCC=VI/O=2.7~3.6V VI/O=1.65~2.7V MIN. MAX. MIN. -0.5 0.8 -0.1 2.0 VI/O+0.3 VI/O-0.4 0.45 VI/O-0.4 0.8VI/O 30 MX25L3237D TEST MAX. UNITS CONDITIONS 0.25VI/O V VI/O+0.4 V 0.2VI/O V VCC=VCCmin VI/O=VI/Omax IOL = -100uA V IOH = -100uA VCC=VCCmin VI/O=VI/Omax REV. 0.02, JUN. 13, 2008 ...
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... Value guaranteed by characterization, not 100% tested in production. 3. tSHSL=15ns from read instruction, tSHSL=50ns from Write/Erase/Program instruction. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set When VI/O<2.7V, tSLCH=25ns, tSHCH=25ns, tSHQZ=20ns (VCC=2.7V~3.6V), tCLQV=26ns, tDVCH=5ns. 6. While VI/O=1.65V~2.7V, fC=40MHz, fT=fQ=33MHz. 7. Test condition is shown as Figure 4, 5. P/N: PM1393 MX25L3237D Min. Typ. D.C. D.C. 5.5 5.5 ...
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... Timing Analysis Figure 6. Serial Input Timing CS# tCHSL SCLK tDVCH SI High-Z SO Figure 7. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1393 tSLCH tCHSH tCHDX tCLCH MSB LSB tCH tCLQV tCL tQLQH tQHQL 32 MX25L3237D tSHSL tSHCH tCHCL tSHQZ LSB REV. 0.02, JUN. 13, 2008 ...
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... Figure 9. Write Enable (WREN) Sequence (Command 06) CS# SCLK SI SO Figure 10. Write Disable (WRDI) Sequence (Command 04) CS# SCLK SI SO P/N: PM1393 Command 06 High Command 04 High-Z 33 MX25L3237D tSHWL REV. 0.02, JUN. 13, 2008 ...
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... MSB MSB command Status Register MSB High-Z 34 MX25L3237D Device Identification Status Register Out REV. 0.02, JUN. 13, 2008 ...
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... BIT ADDRESS DATA OUT MSB 35 MX25L3237D Data Out 1 Data Out DATA OUT MSB MSB REV ...
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... SCLK 8 Bit Instruction EB(hex) SI/SIO0 High Impedance SO/SIO1 High Impedance WP#/SIO2 High Impedance NC/SIO3 P/N: PM1393 MX25L3237D dummy 12 BIT Address cycle address dummy bit6, bit4, bit2...bit0, bit6, bit4.... bit22, bit20, bit18...bit0 address dummy bit23, bit21, bit19 ...
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... P4 P0 bit4, bit0, bit4.... data P5 P1 bit5 bit1, bit5.... data P6 P2 bit6 bit2, bit6.... data P7 P3 bit7 bit3, bit7.... 37 MX25L3237D n Data Output data bit4, bit0, bit4.... data bit5 bit1, bit5.... data bit6 bit2, bit6.... data bit7 bit3, bit7.... REV. 0.02, JUN. 13, 2008 ...
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... Command 6 Address cycle MX25L3237D Data Byte MSB Data Byte 256 MSB ...
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... Byte 0, Byte1 status ( Command 24 Bit Address MSB Command 24 Bit Address MSB 39 MX25L3237D data in 04 (hex) 05 (hex REV. 0.02, JUN. 13, 2008 ...
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... DP Command B9 Stand-by Mode Dummy Bytes MSB Electronic Signature Out MSB Deep Power-down Mode 40 MX25L3237D Deep Power-down Mode RES2 Stand-by Mode REV. 0.02, JUN. 13, 2008 ...
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... Dummy Bytes Manufacturer MSB MSB 41 MX25L3237D Stand-by Mode 47 Device MSB REV. 0.02, JUN. 13, 2008 ...
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... The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1393 Chip Selection is Not Allowed tVSL Read Command is tPUW 42 MX25L3237D Device is fully allowed accessible time Min. Max. Unit ...
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... For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1393 tCHSL tSLCH tDVCH tCHDX MSB IN High Impedance Figure A. AC Timing at Device Power-Up Notes 1 43 MX25L3237D tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN Min. Max. Unit 20 500000 us/V ...
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... The maximum chip programming time is evaluated under the worst conditions of 0C, VCC=3.0V, and 100K cycle with 90% confidence level. LATCH-UP CHARACTERISTICS Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1393 MX25L3237D Min. TYP. (1) Max. (2) 40 100 90 300 ...
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... ORDERING INFORMATION PART NO. CLOCK (MHz) MX25L3237DMI-12G 86 MX25L3237DZNI-12G 86 Note: The followed 86MHz only when VI/O>=2.7V. P/N: PM1393 OPERATING STANDBY Temperature PACKAGE Remark CURRENT MAX. CURRENT MAX. (mA) (uA -40 C~85 C 16-SOP 25 20 -40 C~ MX25L3237D Pb-free 8-WSON Pb-free (6x5 mm) REV. 0.02, JUN. 13, 2008 ...
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... M P/N: PM1393 OPTION: G: Pb-free SPEED: 12: 86MHz (when VI/O>2. will be 40/33MHz when VI/O<2.7V) TEMPERATURE RANGE: I: Industrial (-40˚ 85˚ C) PACKAGE: M: 300mil 16-SOP ZN: WSON (0.8mm package height) DENSITY & MODE: 3237D: 32Mb Serial Flash with VI/O TYPE DEVICE: 25: Serial Flash 46 MX25L3237D REV. 0.02, JUN. 13, 2008 ...
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... PACKAGE INFORMATION P/N: PM1393 MX25L3237D 47 REV. 0.02, JUN. 13, 2008 ...
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... P/N: PM1393 MX25L3237D 48 REV. 0.02, JUN. 13, 2008 ...
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... VI/O into two parts: VI/O<2.5V and VI/O > 2.5V 0.02 1. Changed tSHSL spec from 30/50ns to 15/50ns 2. Add 6x5mm WSON package 3. Modified DC voltage spec 4. VI/O into two parts: VI/O<2.7 and VI/O>2.7 5. Changed Fast Read spec from 40MHz to 33MHz for 2 I/O and 4 I/O P5,31 6. Modified Figure 5 (R1/R2) P/N: PM1393 MX25L3237D Page P5,28,29,30 APR/07/2008 P44,45 P30 P6,8,30,45,47 P31 P5,28,29,30,46 P28 ...
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... Macronix's products in the prohibited applications ACRONIX NTERNATIONAL Headquarters Macronix America, Inc. Macronix Japan Cayman Islands Ltd. Macronix (Hong Kong) Co., Limited. http : //www.macronix.com C L O., TD. Taipei Office Macronix Europe N.V. Singapore Office MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 50 MX25L3237D ...