mx25l8005 Macronix International Co., mx25l8005 Datasheet
mx25l8005
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mx25l8005 Summary of contents
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... JEDEC 1-byte manufacturer ID and 2-byte Device ID - RES command, 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte Device ID HARDWARE FEATURES • SCLK Input - Serial clock input • SI Input - Serial Data Input • SO Output - Serial Data Output P/N: PM1237 MX25L8005 8M-BIT [x 1] CMOS SERIAL FLASH 1 REV. 2.0, APR. 18, 2008 ...
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... All Pb-free devices are RoHS Compliant GENERAL DESCRIPTION The MX25L8005 is a CMOS 8,388,608 bit serial Flash memory, which is configured as 1,048,576 x 8 internally. The MX25L8005 feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS# input ...
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... BLOCK DIAGRAM Address Generator SI CS# SCLK P/N: PM1237 Memory Array Page Buffer Data Register Y-Decoder SRAM Buffer Mode State HV Logic Machine Generator Clock Generator 3 MX25L8005 Output Sense Amplifier Buffer SO REV. 2.0, APR. 18, 2008 ...
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... DATA PROTECTION The MX25L8005 are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences ...
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... BP0 P/N: PM1237 Protect level 8Mb 0 (none) None 1 (1 block) Block blocks) Block 14- blocks) Block 12- blocks) Block 8-15 5 (All) All 6 (All) All 7 (All) All 5 MX25L8005 REV. 2.0, APR. 18, 2008 ...
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... The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. P/N: PM1237 MX25L8005 Hold Hold Condition ...
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... RDP (Page (Deep (Release Program) Power from Deep Down) Power-down) 02 Hex B9 Hex AB Hex AD1 AD2 AD3 7 MX25L8005 READ Fast Read (read data) (fast read data) 03 Hex 0B Hex AD1 AD1 AD2 AD2 AD3 AD3 x n bytes read out CS# goes high ...
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... P/N: PM1237 MX25L8005 8 REV. 2.0, APR. 18, 2008 ...
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... CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is supported. P/N: PM1237 shift in MSB 9 MX25L8005 shift out MSB REV. 2.0, APR. 18, 2008 ...
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... The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte followings: 14(hex) for MX25L8005. The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data out on SO -> ...
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... BP2 BP1 BP0 the level of the level of the level of protected protected protected block block block (note 1) (note 1) (note 1) 11 MX25L8005 bit 1 bit 0 WEL WIP (write enable (write in progress latch) bit) 1=write enable 1=write operation 0=not write 0=not in write enable operation REV. 2.0, APR. 18, 2008 ...
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... When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0 software protected mode (SPM) P/N: PM1237 MX25L8005 WP# and SRWD bit status WP#=1 and SRWD bit=0, or ...
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... Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS# goes high. (see Figure 19) P/N: PM1237 MX25L8005 13 REV. 2.0, APR. 18, 2008 ...
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... If less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low-> sending PP instruction code-> 3-byte address on SI-> at least 1-byte on data on SI-> CS# goes high. (see Figure 18) P/N: PM1237 MX25L8005 14 REV. 2.0, APR. 18, 2008 ...
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... CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode. P/N: PM1237 MX25L8005 15 REV. 2.0, APR. 18, 2008 ...
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... The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table of ID Definitions: RDID Command manufacturer ID C2 RES Command REMS Command P/N: PM1237 memory type 20 electronic ID 13 manufacturer MX25L8005 memory density 14 device ID 13 REV. 2.0, APR. 18, 2008 ...
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... At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress. P/N: PM1237 MX25L8005 17 REV. 2.0, APR. 18, 2008 ...
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... During voltage transitions, all pins may overshoot to -0.5V to 4.6V 4.6V or -0.5V for period up to 20ns. 4. All input and output pins may overshoot to VCC+0.5V -0.5V to 4.6V while VCC+0.5V is smaller than or equal to 4.6V. Figure 4. Maximum Positive Overshoot Waveform 4.6V 3.6V MIN. TYP 18 MX25L8005 20ns MAX. UNIT CONDITIONS 6 pF VIN = VOUT = 0V REV. 2.0, APR. 18, 2008 ...
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... DEVICE UNDER TEST P/N: PM1237 Output timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time are <5ns 2.7K ohm CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT CL=30pF Including jig capacitance (CL=15pF Including jig capacitance for 86MHz and 70MHz) 19 MX25L8005 0.5VCC +3.3V REV. 2.0, APR. 18, 2008 ...
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... V 0.7VCC VCC+0.4 V 0.4 V VCC-0 MX25L8005 TEST CONDITIONS VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VIN = VCC or GND CS# = VCC VIN = VCC or GND CS# = VCC f=86MHz and 70MHz SCLK=0.1VCC/0.9VCC, SO=Open f=66MHz SCLK=0.1VCC/0.9VCC, SO=Open f=33MHz SCLK=0 ...
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... Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set Test condition is shown as Figure 3. P/N: PM1237 for Commercial grade, VCC = 2.7V ~ 3.6V) @33MHz 30pF @86MHz/70MHz 15pF or @66MHz 30pF 21 MX25L8005 Min. Typ. Max. Unit 1KHz 70 & 86 MHz (Condition:15pF) 66 ...
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... Write Inhibit Voltage Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1237 MX25L8005 Min 1.5 22 Max ...
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... Figure 7. Serial Input Timing CS# tCHSL SCLK tDVCH SI High-Z SO Figure 8. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1237 tSLCH tCHSH tCHDX tCLCH MSB LSB tCH tCL tCLQV tQLQH tQHQL 23 MX25L8005 tSHSL tSHCH tCHCL tSHQZ LSB REV. 2.0, APR. 18, 2008 ...
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... HOLD "don't care" during HOLD operation. Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tWHSL CS SCLK SI High-Z SO P/N: PM1237 tHLCH tCHHL tCHHH tHLQZ MX25L8005 tHHCH tHHQX tSHWL REV. 2.0, APR. 18, 2008 ...
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... High-Z SO P/N: PM1237 Command 06 High Command 04 High Manufacturer Identification MSB MSB 25 MX25L8005 Device Identification REV. 2.0, APR. 18, 2008 ...
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... Status Register MSB High 24-Bit Address MSB 7 MSB 26 MX25L8005 Status Register Out MSB Data Out 1 Data Out REV ...
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... P/N: PM1237 BIT ADDRESS DATA OUT MSB MSB 27 MX25L8005 DATA OUT MSB REV. 2.0, APR. 18, 2008 ...
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... Address MSB MSB Data Byte MSB 28 MX25L8005 Data Byte Data Byte 256 MSB REV. 2.0, APR. 18, 2008 ...
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... Figure 20. Block Erase (BE) Sequence (Command 52 or D8) CS# SCLK SI Note: BE command D8(hex). P/N: PM1237 Command 24 Bit Address MSB Command 24 Bit Address MSB 29 MX25L8005 REV. 2.0, APR. 18, 2008 ...
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... DP Command B9 Stand-by Mode Dummy Bytes MSB Electronic Signature Out MSB Deep Power-down Mode 30 MX25L8005 Deep Power-down Mode Sequence RES2 Stand-by Mode REV. 2.0, APR. 18, 2008 ...
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... Dummy Bytes Manufacturer MSB MSB 31 MX25L8005 Stand-by Mode 47 Device MSB REV. 2.0, APR. 18, 2008 ...
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... Figure 26. Power-up Timing (max) Program, Erase and Write Commands are Ignored Chip Selection is Not Allowed V CC (min) Reset State of the Flash V WI P/N: PM1237 MX25L8005 tVSL Read Command is Device is fully allowed accessible tPUW 32 time REV. 2.0, APR. 18, 2008 ...
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... For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1237 tSLCH tDVCH tCHDX MSB IN High Impedance Figure A. AC Timing at Device Power-Up Notes 1 33 MX25L8005 tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN Min. Max. Unit 0.5 500000 us/V REV ...
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... Input Voltage with respect to GND on ACC Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1237 MX25L8005 Min. TYP. (1) Max. ( ...
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... ORDERING INFORMATION PART NO. CLOCK (MHz) MX25L8005MC-15G 70 MX25L8005M2C-15G 70 MX25L8005PC-15G 70 MX25L8005ZMC-15G 70 MX25L8005MI-15G 70 MX25L8005M2I-15G 70 MX25L8005ZMI-15G 70 MX25L8005MI-12G 86 MX25L8005M2I-12G 86 MX25L8005ZNI-12G 86 MX25L8005ZUI-12G 86 Note: 1. 8-land USON is in development. 2. 8-land SON is not recommended for new design. P/N: PM1237 OPERATING STANDBY Temperature PACKAGE CURRENT(mA) CURRENT(uA ...
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... C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: ZM: SON (1.0mm package height) ZN: WSON (0.8mm package height) ZU: USON (0.6mm package height) M: 150mil 8-SOP M2: 200mil 8-SOP P: 300mil 8-PDIP DENSITY & MODE: 8005: 8Mb TYPE DEVICE: 25: Serial Flash 36 MX25L8005 REV. 2.0, APR. 18, 2008 ...
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... PACKAGE INFORMATION P/N: PM1237 MX25L8005 37 REV. 2.0, APR. 18, 2008 ...
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... P/N: PM1237 MX25L8005 38 REV. 2.0, APR. 18, 2008 ...
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... P/N: PM1237 MX25L8005 39 REV. 2.0, APR. 18, 2008 ...
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... P/N: PM1237 MX25L8005 40 REV. 2.0, APR. 18, 2008 ...
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... P/N: PM1237 MX25L8005 41 REV. 2.0, APR. 18, 2008 ...
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... P/N: PM1237 MX25L8005 42 REV. 2.0, APR. 18, 2008 ...
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... REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" 2. Improved tVSL spec from 30us to 10us separated from MX25L4005, MX25L8005 to MX25L8005 1.1 1. Standby current is reduced from 50uA(max.) to 10uA(max.) 2. Added description about Pb-free device is RoHS compliant 3. Improved erase speed: 4KB sector: 90ms(typ.)/270ms(max.)-->60ms(typ.)/120ms(max.) 64KB sector:1s(typ.)/3s(max.)-->1s(typ.)/2s(max.) chip sector:10s(typ.)/20s(max.)--> ...
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... Macronix's products in the prohibited applications ACRONIX NTERNATIONAL Headquarters Macronix America, Inc. Macronix Japan Cayman Islands Ltd. Macronix (Hong Kong) Co., Limited. http : //www.macronix.com C L O., TD. Taipei Office Macronix Europe N.V. Singapore Office MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 44 MX25L8005 ...