k4d551638h Samsung Semiconductor, Inc., k4d551638h Datasheet

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... K4D551638H 256Mbit GDDR SDRAM Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...

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... K4D551638H Revision History Revision Month Year 0.0 July 2005 0.1 September 2005 0.2 November 2005 1.0 January 2006 1.1 April 2006 1.2 April 2006 1.3 April 2007 - Target Spec - Defined Target Specification - Preliminary Spec - Changed CL from 4clk to 3clk of -LC40 - Added current spec - Added IBIS data - Final Spec - Deleted -LC33/36/60 spec. ...

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... GENERAL DESCRIPTION FOR 4M x 16Bit x 4 Bank GDDR SDRAM The K4D551638H is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized 4,194,304 words by 16 bits, fab- ricated with SAMSUNG s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high perfor- ’ ...

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... K4D551638H 4.0 PIN CONFIGURATION PIN DESCRIPTION CK,CK Differential Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe CAS Column Address Strobe WE Write Enable L(U)DQS Data Strobe L(U)DM Data Mask RFU Reserved for Future Use (Top View DDQ ...

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... K4D551638H 5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type *1 Input CK, CK CKE Input CS Input RAS Input CAS Input WE Input LDQS,UDQS Input/Output LDM,UDM Input DQ0 ~ DQ15 Input/Output BA0, BA1 Input A0 ~ A12 Input V /V Power Supply Power Supply DDQ SSQ V Power Supply REF No connection/ ...

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... K4D551638H 6.0 BLOCK DIAGRAM (4Mbit x 16I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 16 Intput Buffer CK, CK Data Input Register Serial to parallel 4Mx16 4Mx16 4Mx16 4Mx16 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS ...

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... K4D551638H 7.0 FUNCTIONAL DESCRIPTION 7.1 Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply V before DDQ - Apply V before V DDQ REF 2. Start clock and maintain stable condition for minimum 200us. ...

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... K4D551638H 7.2 MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different appli- cations ...

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... K4D551638H 7.3 EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. ...

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... K4D551638H 7.4 WRITE INTERRUPTED BY A READ & burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM ...

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... K4D551638H 9.0 AC & DC OPERATING CONDITIONS 9.1 POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to V Parameter Device Supply voltage Output Supply voltage Reference voltage Termination voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage ...

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... K4D551638H 9.3 AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to V Parameter Input High (Logic 1) Voltage; DQ Input Low (Logic 0) Voltage; DQ Clock Input Differential Voltage; CK and CK Clock Input Crossing Point Voltage; CK and CK Note : the magnitude of the difference between the input level on CK and the input level on CK. ...

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... K4D551638H 9.5 CAPACITANCE Parameter Input capacitance( CK Input capacitance ~ Input capacitance( CKE, CS, RAS,CAS Data & DQS input/output capacitance(DQ Input capacitance(DM0 ~ DM3) DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Parameter Decoupling Capacitance between V DD Decoupling Capacitance between V ...

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... Power down exit time Refresh interval time Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM AC CHARACTERISTICS (II) K4D551638H-LC40 Frequency Cas Latency 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 K4D551638H-LC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 2.5 Symbol Min tRC 13 tRFC ...

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... K4D551638H Write Interrupted by a Read & burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM ...

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... K4D551638H 10.0 IBIS : I/V Characteristics for Input and Output Buffers (1) Full Strength Driver Characteristics Pulldown Current (mA) Voltage Minimum (V) 0.0 0 0.1 4.8 0.2 9.6 0.3 14.4 0.4 19.1 0.5 23.9 0.6 28.8 0.7 33.5 0.8 38.3 0.9 41.2 1.0 44.3 1.1 46.6 1.2 48.0 1.3 49.0 1.4 49.3 1.5 49.6 1.6 49.9 1.7 50.3 1.8 50.9 1.9 51.1 2.0 51.4 2.1 51.6 2.2 51.8 2.3 51.9 2.4 52.0 2.5 52.2 2.6 52.4 2.7 52.5 Maximum Minimum 0 0 10.0 -4.8 18.9 -9.6 27.0 -14.4 35.3 -19.1 43.5 -23.9 51.4 -28.8 59.1 -33.5 65.7 -37.4 72.7 -39.7 79.4 -40.2 85.8 -40.6 91.8 -40.6 97.6 -41.0 103.1 -41.2 108.0 -41.5 112.7 -41.7 116.6 -41.8 120.5 -41.9 124.4 -42.0 128.2 -42.1 131.6 -42.2 134.7 -42.3 137.7 -42.4 140.4 -42.5 142.8 -42.6 144.8 -42.7 146.4 -42 256M GDDR SDRAM Pullup Current (mA) Maximum 0 -10.4 -20.8 -31 ...

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... K4D551638H 10.0 IBIS : I/V Characteristics for Input and Output Buffers (2) Weak Strength Driver Characteristics Pulldown Current (mA) Voltage Minimum (V) 0.0 0 0.1 2.7 0.2 5.4 0.3 8.1 0.4 10.8 0.5 13.5 0.6 16.3 0.7 18.9 0.8 21.6 0.9 23.3 1.0 25.1 1.1 26.4 1.2 27.2 1.3 27.7 1.4 27.9 1.5 28.1 1.6 28.3 1.7 28.5 1.8 28.8 1.9 28.9 2.0 29.1 2.1 29.2 2.2 29.3 2.3 29.4 2.4 29.4 2.5 29.5 2.6 29.6 2.7 29.7 Maximum Minimum 0 0 5.2 -2.7 10.3 -5.4 15.2 -8.1 20.0 -10.8 24.5 -13.5 29.1 -16.3 33.5 -18.9 37.2 -21.2 41.1 -22.5 44.9 -22.8 48.6 -23.0 52.0 -23.1 55.2 -23.2 58.3 -23.3 61.0 -23.5 63.9 -23.6 66.0 -23.6 68.2 -23.7 70.4 -23.8 72.6 -23.8 74.5 -23.9 76.2 -24.0 77.9 -24.1 79.5 -24.1 80.8 -24.1 82.0 -24.2 82.9 -24 256M GDDR SDRAM Pullup Current (mA) Maximum 0 -5.2 -10.3 -15.2 -20.0 -24.5 -29.1 -33.5 -37.2 -41.1 -44.9 -48.6 -52.0 -55.2 -58.3 -61.0 -63.9 -66.0 -68.2 -70.4 -72.6 -74.5 -76.2 -77.9 -79.5 -80.8 -82.0 -82.9 Rev. 1.3 April 2007 ...

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... K4D551638H 11.0 PACKAGE DIMENSIONS (66pin TSOP-II) #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’Y OUT QUALITY #34 #33 22.22±0.10 (10×) 0.65TYP 0.30±0.08 0.65±0.08 (10× 256M GDDR SDRAM Units : Millimeters (10×) (10×) +0.075 0.125 -0.035 0.10 MAX 0.25TYP [ ] 0.075 MAX 0×~8× Rev. 1.3 April 2007 ...