com90c66 Standard Microsystems Corp., com90c66 Datasheet
com90c66
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com90c66 Summary of contents
Page 1
... ARCNET logic found in Standard Microsystems' original COM90C26 and COM90C32 with an on-chip RAM, as well as the 16-bit data bus interface for the IBM PC/AT. Because of the inclusion of the RAM buffer in the COM90C66, a complete ARCNET node can be implemented with only one or two ...
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... Please see Addendum 1 entitled Data Sheet Errata for Revision B COM90C66, which discusses changes to this data sheet which apply to the Revision B device, on Page 62. Please see Addendum 2 entitled Data Sheet Errata for Revision D COM90C66, which discusses changes to this data sheet which apply to the Revision D device, on Page 64. ...
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... The COM90C66 configuration and automatically reconfigures the token passing order as new nodes are added or deleted from the network. The COM90C66 performs address recognition, CRC checking acknowledgement, management each interfaces directly to the IBM PC/AT or compatibles ...
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... When these signals are high, data gets sent from the PC to the COM90C66. When these signals are low, data gets sent from the COM90C66 to the PC, or from the PROM to the PC if the PROM signal is also low. Output. This signal, when low, is optionally used by the COM90C66 to extend host cycles ...
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... Input. This active low signal is issued by the host microprocessor to indicate a Memory Write operation. A low pulse on this pin when the COM90C66 is accessed enables data from the data bus into the internal RAM of the COM90C66. Input. This active high signal is the power on reset signal from the host ...
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... This is an open-drain signal. An external pull-up resistor is typically provided by the system. Input. This active low signal is used to enable the COM90C66 to transfer data on D8-D15 of the Data Bus. Output. These active low signals carry the transmit data information, encoded in pulse COM90C66 to the LAN Driver ...
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DESCRIPTION OF PIN FUNCTIONS PLCC PIN NO. NAME SYMBOL 33, 34 Crystal XTAL1, Oscillator XTAL2 59 CA Clock CACLK 58 Clock CLK 1, 43 Power Supply V cc 21, 68 Ground GND 60-61 No Connect NC DESCRIPTION An external parallel ...
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... Increment N Y ACK? Set TMA *The ID set by the external switches is continually sampled during COM90C66 operation refers to the identification number of the ID assigned to this node. - NID refers to the next identification number that receives the token after this ID passes it. - SID refers to the source identification. ...
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... INVITATIONS TO TRANSMIT will be sent to all 256 possible IDs. Each COM90C66 on the network will finally have saved a NID value equal to the ID of the COM90C66 that it released control to. At this point, control is passed directly from one node to the next with no wasted INVITATIONS TO TRANSMIT being sent to IDs ...
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... During NETWORK activity will appear on the line every 82 µS. This 82 µS is equal to the Response Time of 74.7 µS plus the time it takes the COM90C66 to retransmit another message (usually another INVITATION TO TRANSMIT). Reconfiguration Time If any node does not receive the token within the Reconfiguration Time, the node will initiate a NETWORK RECONFIGURATION ...
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The line idles in a spacing (logic "0") condition. A logic "0" is defined as no line activity and a logic "1" is defined as ...
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... PROM Read Cycles. The microprocessor's control bus is directly connected to the COM90C66 and is used in access cycle communication between the device and the microprocessor. All accesses support zero wait state arbitration in most machines. ...
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... The COM90C66 derives a 5 MHz and a 2.5 MHz clock from the external crystal. These clocks provide the rate at which the instructions are executed within the COM90C66. clock is the rate at which the program counter operates, while the 2.5 MHz clock is the rate at which the instructions are executed ...
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... Twisted Pair circuitry shown. Memory I/O Node ID For COAX circuitry, see Base Address Select Switch Select Switch HYC9058/68 data sheets IOS0-2 MS0-4 NID0-7 XTAL1 XTAL2 C8 nPULSE2 18 nPULSE1 20 RXIN 7 17 SMSC 19 COM90C66 CLK N/C 4 N/C CACLK -5V nTXLED nBSLED CC +5V 1 ROM C9 2 ENABLE R1-R4 = 5.6K, 1/2 W ...
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IOS0-2 MS0-4 A0-A19 nENROM nPROM ADDRESS AEN DECODING BALE CIRCUITRY nTOPL nTOPH D0-D15 STATUS/ INTR COMMAND REGISTER RESET RESET IN LOGIC nMEMR nMEMW I/O CHANNEL nIOR READY nIOW AND BUS nMEMCS16 ARBITRATION nIOCS16 CIRCUITRY IOCHRDY nSBHE nOWS FIGURE 3 - ...
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BALE A19 A18 A17 A16 Transparent A15 Latch A14 A13 A12 A11 FIGURE 4 – MEMORY SELECTOR nENROM BALE A19 A18 A17 Transparent A16 Latch A15 A14 A13 I/O 16K X 8 Mode, A13 is a Don't Care ...
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FIGURE 7 - 16K MEMORY SEGMENT CHOSEN BY MS0-MS4 (Memory Mapped Mode) SHORT PACKET FORMAT (256 OR 512 BYTE PAGE) SID 0 DID 1 COUNT = 256-N 2 NOT USED COUNT DATA BYTE 1 DATA BYTE 2 DATA BYTE N-1 ...
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Table 1 – User Configuration of Memory Map DECODED BITS FOUND IN DATA REGISTER MS4 MS3 MS2 MS1 MS0 ...
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... PROM. The nENROM pin is used to enable decoding for the on-board PROM. If nENROM is connected to a logic "1", the COM90C66 will not generate the nPROM signal, the nTOPL signal, or the IOCHRDY signal for accesses to the PROM. In this configuration, the COM90C66 will only occupy a 2K segment of memory ...
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Table 3 – Read Register Summary REGISTER MSB STATUS DIAG. MYRECON X RCVACT TOKEN STATUS CONFIG- CCHEN DECODE ET1 16EN URATION I/O SELECT 0 0 I/O5 MEMORY MEM7 MEM6 MEM5 SELECT NODE NID7 NID6 NID5 ID RESERVED ...
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Table 4 – Write Register Summary ADDRESS MSB CCHEN DECODE ET1 16EN NID7 NID6 NID5 ...
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... The Status Register defaults to the value 1XX1 0001 upon either hardware or software reset. Interrupt Mask Register (IMR) The COM90C66 is capable of generating an interrupt signal when certain status bits become true. A write to the IMR specifies which status bits will be enabled to generate the interrupt. ...
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... Interrupt Mask Register is also set. This bit is undefined. This bit is undefined. This bit, if high, indicates that the COM90C66 has been reset by either a software reset, a hardware reset, or setting the Node ID = 00H. The POR bit is cleared by the CLEAR FLAGS command ...
Page 24
... COM90C66 next receives the token. This command will cancel command. If the COM90C66 is not yet receiving a packet, the RI (Receiver Inhibited) bit will be set to logic "1" the next time the token is received. If packet reception is already underway, reception will run to its normal conclusion. 24 ...
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... If the value of "c" logic "1", the COM90C66 will handle long as well as short packets. If the value of "c" logic "0", the COM90C66 will only handle short packets (packets less than 254 bytes). ...
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Table 8 - Configuration Register BIT BIT NAME SYMBOL 7 16-Bit Enable 16EN 6 Command CCHEN Chaining Enable 5 Decode Mode DECODE In I/O Mapped applications, this bit is used to choose 4, 3 Extended ET1, ET2 These bits allow ...
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... RAM for memory mapped accesses. This bit defaults to a logic "0" upon hardware reset. A logic "1" on this bit disables the transmitter of the COM90C66, while the receiver remains functional. A logic "0" keeps the transmitter enabled. diagnostic troubleshooting of the network or node. Refer to the Improved Diagnostics section of this document for further details. This bit defaults to a logic " ...
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... ID. To enter this special mode, the Node ID switches must be set to 00H. Note that when the Node ID switches are set to 00H, the COM90C66 is put into a Disable Transmitter mode and it will not attempt to join the network. When the device is in the Disable Transmitter mode, tokens are ...
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... Zero Wait-State signal, the diagnostic pins, and the choice of Memory or I/O Mapped functionality. Fourthly, the COM90C66 is very high speed. The ability of the device to implement zero wait state cycles is partly due to the fact that the RAM is internal to the device. ...
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... The SID in Address 0 is used by the receiving node to reply to the transmitting node. The COM90C66 puts the local ID in this location, therefore not necessary to write into this location. Please note that a short packet may contain between one and 253 data bytes, while a long packet may contain between 257 and 508 data bytes ...
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... RAM buffer other than the SID and DID. Once the packet is received and stored correctly in the selected buffer, the COM90C66 sets the RI bit to logic "1" to signal the microprocessor that the reception is complete. SOFTWARE COMPATIBILITY ...
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... FIFO, commands to be transmitted and received, as well as the status bits, are pipelined. In order for the COM90C66 to be compatible with previous SMSC ARCNET devices, the device defaults to the non-chaining mode. In order to take advantage of the Command Chaining operation, the Command Chaining Mode must be enabled via a logic " ...
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... TRANSMIT TO PAGE nn command, COM90C66 responds in the usual manner by resetting the TA and TMA bits to prepare for the transmission from the specified page. The TA bit can be used to see if there is currently a transmission pending, but the TA bit is really meant to be used in the non-chaining mode only. ...
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... A minimum of 200nS interrupt inactive time interval is guaranteed. In the COM90C66, the Receive Inhibit (RI) bit of the Interrupt Mask Register now masks only the TRI bit of the Status Register, not the RI bit as in the non-chaining mode. Since the TRI bit is only ...
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... Upon reset, the transmitter portion of the device is disabled and the internal registers assume those states outlined in the Internal Registers section. The COM90C66 will start 102.4 µS after the RESET IN signal is removed. Please note that the internal RAM buffer cannot be seen by the processor unless a software reset is issued. ...
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Hardware or Software Reset Internal POR nMEMR, nMEMW, nIOR, nIOW Microsequencer POR Internal Reset 1 During this time, the microsequencer is being reset and the transmitter portion of the device is disabled. 2 During this time, the microsequencer writes D1H ...
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... KByte block of memory. The unlatched version of the nMEMCS16 mode of the COM90C66 will meet the timing specification of nMEMCS16 for every machine, but the limitations are that this mode may complicate co-existence with other 8- ...
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... If the optional PROM is on board, it might require a slower cycle to accommodate its access time even if the device is configured for Zero Wait State Mode. signal is active (logic "0"), the COM90C66 will negate the IOCHRDY signal for two XTAL1 clocks on ROM read accesses. If the optional external ...
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Data Register I/O Address ODH High D0-D15 Address Pointer Register I/O Address 0FH High 11-Bit Counter FIGURE 11 - SEQUENTIAL I/O MAPPED MEMORY ACCESS OPERATION Memory I/O Address 0CH Data Bus Low 16 I/O Address 0EH Low Memory Address Bus ...
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A11-A19 SA11-SA19 TRANSPARENT LATCH BALE Falling Edge of BALE Latches the Address Rising Edge of BALE Makes Latch Transparent LA17-LA19 3 5 MS0-MS4 FIGURE 12 – nMEMCS16 GENERATION AEN 12 TRANSPARENT SA4-SA15 LATCH BALE IOS0-IOS2 2 SA2-SA3 FIGURE 12A ...
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... In the case where the COM90C66 spec meets the bus speed and the user does not need to "speed up" or "slow down" the bus, neither the nOWS nor the IOCHRDY signal should be used. In this case, the Wait State bit of the Configuration Register should be reset to logic " ...
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Data Register space is desired, the A0 bit should be forced to a logic "0" and A1-A10 will be used to load the Address Pointer Register. A single byte ...
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... NODE ID LOGIC The Node ID code generated by the external Node ID Select Switches is used to identify this particular COM90C66. The code, which is input by the COM90C66 in parallel format, is used by the COM90C66 during transmission, reception, reset, and reconfiguration. Upon reset, the COM90C66 reads the Node ID code set up on the switches and loads them into the Node ID Register ...
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... In addition to the Diagnostic Status Register bits, the COM90C66 contains two pins for direct connection to LED's. These pins are meant to immediately provide basic visual information on board and network activity with decreased dependence upon software. The COM90C66 contains an internal retriggerable digital one- ...
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... DIPULSE 400ns RXIN FIGURE 13 - DIPULSE GENERATION AND RECEIVE WAVEFORM FOR DATA OF 1-1-0 The COM90C66 crystal oscillator has been designed to work with a parallel resonant crystal. Only two capacitors are needed (one from each leg of crystal to ground). The values The of the capacitors are two times the lead capacitance of the crystal ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS * Operating Temperature Range ......................................................................................... 0 Storage Temperature Range ....................................................................................... -55 Lead Temperature (soldering, 10 seconds) ............................................................................... +325 Positive Voltage on any pin, with respect to ground ................................................................ V Negative Voltage on any pin, with ...
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DC ELECTRICAL CHARACTERISTICS (T PARAMETER SYMBOL Low to High Threshold V ILH Input Voltage (RESET, AEN, nIOR, nIOW, nMEMR, nMEMW) High to Low Threshold V IHL Input Voltage (RESET, AEN, nIOR, nIOW, nMEMR, nMEMW) Low Output Voltage 1 V OL1 ...
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CAPACITANCE ( 1MHz Output and I/O pins capacitive load specified as follows: PARAMETER SYMBOL Input Capacitance C IN Output Capacitance 1 C OUT1 (All outputs except IOCHRDY, n0WS, nMEMCS16, nIOCS16, INTR) ...
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The AC parameters in Figures 14-26 are preliminary. Enhancements will follow. nMEMR, nMEMW, nIOR, or nIOW t2 nOWS** t4 IOCHRDY** Parameter t1 Control Signal Pulse Width t2 Control Signal Low to nOWS Low t3 Control Signal High to nOWS High ...
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... High to BALE High (Next Address) t11 Address, nSBHE Invalid to nMEMCS16 High (Unlatched)* * For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address Mode. ** 130nS minimum inactive time on consecutive memory reads from the COM90C66. FIGURE 15 - READ RAM CYCLE VALID t2 VALID DATA ...
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... High to BALE High (Next Address) t9 Address, nSBHE Invalid to nMEMCS16 High * For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address Mode. ** 200nS minimum inactive time on consecutive memory writes to the COM90C66. FIGURE 16 - WRITE RAM CYCLE VALID t2 t4 VALID DATA ...
Page 52
... High to BALE High (Next Address) AEN Hold after nIOR High t10 * For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address Mode. ** 130 nS minimum inactive time on consecutive reads from Data Register of the COM90C66. FIGURE 17 - READ I/O CYCLE VALID t2 VALID DATA ...
Page 53
... High to BALE High (Next Address) t8 AEN Hold after nIOW High * For latched address, t1 and t2 do not apply. Please refer to Figure 21 for Latched Addresss Mode. ** 200 nS minimum inactive time on consecutive writes to the Data Register of the COM90C66. FIGURE 18 - WRITE I/O CYCLE VALID t2 t4 ...
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A0-A19 t1 BALE nMEMR t3 nPROM ** nTOPL IOCHRDY Parameter t1 Address Set Up to BALE Low * t2 Address Hold after BALE Low * t3 Address, Set Up to nMEMR Low t4 nMEMR Low to nPROM Low nMEMR Low ...
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AEN A0-A15 t1 BALE nIOW t3 nPROM ** IOCHRDY Parameter t1 Address Set Up to BALE Low * t2 Address Hold after BALE Low * t3 Address, AEN Set Up to nIOW Low t4 nIOW Low To nPROM Low t5 ...
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BALE (tied high) A0-A19 nMEMR nMEMW nIOR nIOW Parameter t1 Control Signal High to Address Invalid In the case of Latched Addresses, when BALE is tied high, disregard t1 and t2 in Figures 15-20. Instead, use the above timing. FIGURE ...
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Parameter t1 nPULSE1, nPULSE2 Pulse Width t2 nPULSE1, nPULSE2 Period t3 nPULSE1, nPULSE2 Overlap *NOTE (crystal period) for clock frequencies other than 20 MHz. **NOTE (crystal ...
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RXIN Parameter t1 RXIN Pulse Width t2 RXIN Period * NOTE: This period applies to data of two consecutive one's. FIGURE 23 - RECEIVE TIMING t2 min typ max units 10 nS 400 nS* 58 ...
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XTAL1 Parameter t1 Input Clock High Time t2 Input Clock Low Time t3 Input Clock Period f Input Clock Frequency FIGURE 24 – TTL INPUT CLOCK TIMING ON XTAL1 PIN t1 CLK Parameter t1 Output Clock High Time t2 ...
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RESET INTR nTXLED nBSLED Parameter t1 Reset Pulse Width t2 INTR Inactive Time t3 nTXLED Active (Low) t4 nBSLED Active (Low) FIGURE 26 - RESET, INTERRUPT, AND LED TIMING min typ 120 200 650 320 60 ...
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G PIN DIM 84L A .165-.179 A1 .095-.109 D 1.185-1.195 D1 1.150-1.156 D2 1.090-1.130 1.000 D3 F .050 TYP G .045 TYP J .010 E .047-.053 R .025-.045 B .013-.021 B1 .027 .020-.045 C FIGURE ...
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... In the Revision B device, the nTXLED active width is only 314 µsec. - These corrections apply to this data sheet only when used for Revision B of the COM90C66. This COM90C66 revision is identified on the part by the letter "B" preceding the date code. Specific entries in table format appear on the following page. ...
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... DATA SHEET ERRATA FOR REVISION B COM90C66 PAGE SECTION/FIGURE/ENTRY 4 Description of Pin Functions - n0WS 13 Figure 2 - Bus Interface 20,21, Tables Configuration 25,37, Register Bit 7 (16EN) and Bit 5 39 (DECODE); Tables 11, 12; Figure 12 31-33 Command Chaining section 34,36 READ AND WRITE CYCLES - Memory vs. I/O Cycles section 37,40 Wait State Details section; Table 13 40 8-Bit vs ...
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... ALE signal should be disregarded. These corrections apply to this data sheet only when used for Revision D of the COM90C66. This COM90C66 revision is identified on the part by either the letter "D" preceding the date code or no letter at all preceding the date code. ...
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... DATA SHEET ERRATA FOR REVISION D COM90C66 PAGE SECTION/FIGURE/ENTRY 2,6,13 Pin Configuration Description of Pin Functions - Pin 60; Figure 2 - System Block Diagram - Pin 60 25 Table 8 - Configuration Register - Bit 7 CORRECTION - Pin 60; In Revisin D, Pin 60 is not a No Connect, but rather, "n16-Bit Detect". "n16DETECT", and the Description should read " ...
Page 66
... Figure 18 - Write I/O Cycle - t5 CORRECTION The following paragraph should be inserted after the heading 8-Bit Vs. 16-Bit Accesses : "The COM90C66 defaults to the appropriate bus- width mode when Pin 60 is connected to a signal which is low only in the presence of a 16-bit bus, such as connector D18 of the AT bus (AT ground) ...
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PAGE SECTION/FIGURE/ENTRY 3 Description of Pin Functions, Pin 53 26 Configuration Register, Bit 2 37,40 Wait State Details section; Table 13 - IOCHRDY and n0WS Signal Behavior 48 Figure 14 - Zero Wait State and IOCHRDY Timing 3 Description of ...
Page 68
PAGE SECTION/FIGURE/ENTRY 49, 50, 53 Figures 15,16,19 - Read RAM Cycle, Write RAM Cycle, Read PROM Cycle CORRECTION For Revision D, a new timing parameter should exist: Address, SBHE hold after Control Low...20 nsec minimum. This parameter is only required ...
Page 69
... Modified Version of Pages 16 and 41 for Rev. D COM90C66 Only. nMEMR,nMEMW BALE A19 A18 A17 A16 Transparent Transparent A15 Latch Latch A14 A13 A12 A11 FIGURE 4 - MEMORY SELECTOR nENROM nMEMR BALE A19 A18 A17 Transparent Transparent A16 Latch Latch A15 A14 A13 I/O 16K X 8 Mode, A13 is a Don't Care ...
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... Modified Version of Page 40 for Rev. D COM90C66 Only. SA11-SA19 A11-A19 LA17-LA19 3 5 MS0-MS4 FIGURE 12 – nMEMCS16 GENERATION AEN SA4-SA15 IOS0-IOS2 2 SA2-SA3 FIGURE 12A - nIOCS16 GENERATION 9 COMPARATOR (for 2K segment) 5 COMPARATOR (for 128K segment) 5 nENROM DECODE 12 COMPARATOR DECODER nMEMCS16 MUX ...
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... For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address Mode ** 130ns minimum inactive time on consective memory reads from the COM90C66. For Revision D devices, if BALE is tied high, then Address, nSBHE must be held for 20nsec *** after nMEMR Low. FIGURE 15 - READ RAM CYCLE ...
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... For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address Mode. ** 200nS minimum inactive time on consecutive memory writes to the COM90C66. *** For Revision D devices, if BALE is tied high, then Address, nSBHE must be held for 20 nsec after nMEMW Low. FIGURE 16 - WRITE RAM CYCLE ...
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... High to BALE High (Next Address) t9 AEN Hold after nIOR High t10 * For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address Mode. 130 nS minimum inactive time on consecutive reads from Data Register of the COM90C66. ** FIGURE 17 - READ I/O CYCLE VALID t2 VALID DATA t4 ...
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... High to BALE High (Next Address) t8 AEN Hold after nIOW High * For latched address, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address Mode. ** 200 nS minimum inactive time on consecutive writes to the Data Register of the COM90C66. FIGURE 18 - WRITE I/O CYCLE VALID t2 t4 ...
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... Modified Version of Page 54 for Rev. D COM90C66 Only. A0-A19 t1 BALE nMEMR t3 nPROM ** nTOPL IOCHRDY Parameter t1 Address Set Up to BALE Low * t2 Address Hold after BALE Low * t3 Address, Set Up to nMEMR Low t4 nMEMR Low to nPROM Low nMEMR Low to nTOPL Low t5 t6 nMEMR Low to IOCHRDY Low ...
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... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. COM90C66 Rev. 09/26/91 ...