ax88796blf ASIX Electronics Corporation, ax88796blf Datasheet - Page 72

• Manufacturer Part Number: ax88796blf
• Description: Low-pin-count Non-pci 8/16-bit 10/100m Fast Ethernet Controller
• Manufacturer: ASIX Electronics Corporation

7.4.5 Burst Reads Access Timing
*
*
FIFO_SEL(SA5)
1
2
Burst read access is enabled when set FIFO_SEL(SA5) is driven high during a read access. This is normally
accomplished by connecting the FIFO_SEL(SA5) signal to a high-order address line. This mode is useful when
the host processor must increment its address when accessing the AX88796B.
In this mode, performance is improved by allowing an unlimited number of back-to-back WORDS read cycles.
AX88796B base on SA0 or SA1 address toggles to identify WORD access cycle time. Host can set burst cycle
base on SA0 or SA1 toggle by BCB1 (CR page3 Offset 0Dh).
: Base on SD bus output load 25pF
: Base on SD bus output load 50pF
SA1 or SA0
Symbol
Tacyc
Tdoff
CSn, RDn
Tdoh
Tdon
Tasu
Tadv
Trdh
Tah
Tdv
SD[15:0]
ADDRESS SETUP TIME
ADDRESS HOLD TIME
DATA VALID TIME FROM RDn
DATA VALID TIME FROM ADDRESS
DATA OUTPUT HOLD TIME
RDn HI REQUIRE TIME
READ CYCLE TIME
DATA BUFFER TURN ON
DATA BUFFER TURN OFF
Tas u
Tacyc
Tacyc
Tdv
Tdon
Description
Tadv
Tacy c
Tacy c
72
Tadv
AX88796BLF / AX88796BLI
Min
ASIX ELECTRONICS CORPORATION
13
48
0
0
0
0
-
Tadv
Typ.
Tacyc
Tacyc
-
-
-
-
-
Tdoh
Max
33*
35*
33*
35*
Tdoff
7
-
-
-
-
Trdh
Trdh
Tah
1
2
1
2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns