ax88790 ASIX Electronics Corporation, ax88790 Datasheet
ax88790
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ax88790 Summary of contents
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... Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88790 also provides an extra IEEE802.3u compliant media-independent interface (MII) to support other media applications. Using MII interface, Home LAN PHY type media can be supported. The AX88790 is built in interface to connect FAX/MODEM chipset with parallel bus interface. ...
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... AX88790 L 1.0 INTRODUCTION .............................................................................................................................................. 5 1 :..................................................................................................................................... 5 ENERAL ESCRIPTION 1.2 AX88790 .............................................................................................................................. 5 LOCK IAGRAM 1.3 AX88790 ONNECTION 2.0 SIGNAL DESCRIPTION ................................................................................................................................... 7 2.1 PCMCIA NTERFACE IGNALS 2.2 EEPROM S G ................................................................................................................................ 8 IGNALS ROUP 2.3 MII INTERFACE SIGNALS GROUP 2.4 10/100M BPS WISTED AIR NTERFACE PINS GROUP 2 PHY LED UILT IN INDICATOR PINS GROUP 2 ...
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... PACKAGE INFORMATION........................................................................................................................... 48 APPENDIX A: APPLICATION NOTE 1 ............................................................................................................. 49 A 25MH ................................................................................................................................. 49 SING RYSTAL Z A 25MH ............................................................................................................................ 49 SING SCILLATOR Z APPENDIX B: POWER CONSUMPTION REFERENCE DATA...................................................................... 50 ERRATA OF AX88790 .......................................................................................................................................... 51 DEMONSTRATION CIRCUIT (A) : AX88790 + HOMEPNA 1M8 PHY.......................................................... 52 DEMONSTRATION CIRCUIT (B) : AX88790 ONLY ....................................................................................... 57 3-in-1 PCMCIA Fast Ethernet Controller .......................................................................................................... 38 . ......................................................................................................... 39 ........................................................................................................................ 40 ................................................................................................................... 40 ....................................................................................................................... 41 3 ASIX ELECTRONICS CORPORATION ...
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... AX88790 AX88790 B D ............................................................................................................................. 5 IG LOCK IAGRAM AX88790 ONNECTION PCMCIA AB BUS INTERFACE SIGNALS GROUP EEPROM AB BUS INTERFACE SIGNALS GROUP MII AB INTERFACE SIGNALS GROUP 10/100M BPS WISTED AIR PHY LED AB UILT IN INDICATOR PINS GROUP ...
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... Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88790 also provides an extra IEEE802.3u compliant media-independent interface (MII) to support other media applications. Using MII interface, Home LAN PHY type media can be supported. The AX88790 is also built in interface to connect FAX/MODEM chipset with parallel bus interface. ...
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... AX88790 L 1.3 AX88790 Pin Connection Diagram The AX88790 is housed in the 128-pin plastic light quad flat pack. See Fig - 2 AX88790 Pin Connection Diagram. GPI[0]/LINK 103 VDD 104 VSS 105 GPI[1]/DPX 106 TX_CLK 107 TX_EN 108 TXD[0] 109 TXD[1] 110 TXD[2] 111 ...
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... Attribute Memory and to the I/O space. 19 I/O Read: The host asserts IORD# to read data from AX88790 I/O space. 18 I/O Write: The host asserts IOWR# to write data into AX88790 I/O space. 20 Output Enable : The OE# line is used to gate Memory Read data from memory on PC Card ...
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... AX88790 L 2.2 EEPROM Signals Group SIGNAL TYPE PIN NO. EECS O EECK O/PD EEDI O EEDO I/PU Tab - 2 EEPROM bus interface signals group 2.3 MII interface signals group SIGNAL TYPE PIN NO. RXD[3:0] I/PU 98 – 95 CRS I/PD RX_DV I/PD RX_ER (Omit) No Support Receive Error: RX_ER is driven by PHY and synchronous to RX_CLK I/PU COL I/PD TX_EN ...
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... AX88790 L 2.4 10/100Mbps Twisted-Pair Interface pins group SIGNAL TYPE PIN NO. TPIP I TPIN I TPOP O TPON O REXT10 I REXT100 I REXTBS I Tab - 4 10/100Mbps Twisted-Pair Interface pins group 2.5 Built-in PHY LED indicator pins group SIGNAL TYPE PIN NO. I_ACT O or I_FULL/COL I_SPEED O I_LINK O Or I_LK/ACT Tab - 5 Built-in PHY LED indicator pins group 2 ...
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... AX88790 L Signal Name Type Pin No. MRDY I/PU MRESET# O MDCS# O/PU MPWDN O/PU MINT I/PD MRIN# I/PU MAUDIO I/PU Tab - 6 Modem interface signals group 2.7 General Purpose I/O pins group Signal Name Type Pin No. GPI[2]/SPD I/PU GPI[1]/DPX I/PU GPI[0]/LINK I/PU Tab – 7 General Purposes I/O pins group 3-in-1 PCMCIA Fast Ethernet Controller ...
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... Reset is active high then place AX88790 into reset mode immediately. During falling edge the AX88790 loads the power on setting data. And, after the falling edge the AX88790 loads the EEPROM data. Test Pins : Active high These pins are just for test mode setting purpose only. Must be pull down or keep no connection when normal operation ...
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... AX88790 L 2.9 Power on configuration setup signals cross reference table Signal Name Share with MPD_SET MPWDN PPD_SET EECK I_OP MDCS# Tab - 9 Power on Configuration Setup Table 3-in-1 PCMCIA Fast Ethernet Controller Description MPD_SET = 0: MPWDN pin active high. MPD_SET = 1: MPWDN pin active low. (default) PPD_SET = 0: Internal PHY in normal mode. (default) PPD_SET = 1: Internal PHY in power down mode ...
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... Note: bit 3 register of LCOR in AX88190 is replaced by bit 0 of CFL in AX88790 Bit 0 of CFL: Enable Power Down mode This bit is set to 1; the LAN will go into power down mode. At power down mode AX88790 will disable MAC transmitting and receiving operation. But the host interface will not be affected. ...
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... AX88790 L 3.3 I/O Mapping SYSTEM I/O OFFSET 0000H 001FH Tab – 12 I/O Address Mapping 3.4 SRAM Memory Mapping OFFSET 0000H 03BFH 03C0H 03C2H 03C4H 03C6H 03CAH 03CCH 03CEH 03DFH 03E0H 03E2H 03E4H 03E6H 03EAH 03ECH 03EEH 03FFH 0400H 0401H 0402H 0403H 0404H 0405H 0406H 07FFH 4000H 7FFFH Tab – ...
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... AX88790 L 4.0 Registers Operation There are four register sets in AX88790: The PCMCIA function configuration registers of LAN. The PCMCIA function configuration registers of MODEM. The MAC core register. The embedded PHY registers. 4.1 PCMCIA Function Configuration Register Set of LAN REGISTER LCOR CONFIGURATION OPTION REGISTER LCSR ...
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... Configuration Option Register of LAN (LCOR) Offset 3C0H (Read/Write) FIELD R/W/C 7 R/W Software Reset Assert this bit will reset the LAN function of AX88790. Return this bit will leave the LAN function of AX88790 in a post-reset state as same as that following hardware reset. The value of this bit power-on. 6 R/W Level IRQ This bit should be set to 1 ...
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... R/W PPwrDwn : PHY power down setting While this bit set to 1, AX88790 will force embedded PHY into power down mode. As for PPWDN is active high or active low. Please refer section 2.9 Power on configuration setup signal cross-reference table. Note: The master control of Power Down mode is place on Bit 0 of CFL. If user want to enable power down mode, must set the relative bit of EEPROM that map to bit 0 of CFL register to logic 1 ...
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... Configuration Option Register of MODEM (MCOR) Offset 3E0H (Read/Write) FIELD R/W/C 7 R/W Software Reset Assert this bit will reset the MODEM function of AX88790. Return this bit will leave the MODEM function of AX88790 in a post-reset state as same as that following hardware reset. The value of this bit power-on. 6 R/W Level IRQ This bit should be set to 1 ...
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... AX88790 L 4.2.2 Configuration and Status Register of MODEM (MCSR) Offset 3E2H (Read/Write) FIELD R/W/C 7:3 - Reserved 2 R/W MPwrDwn : Modem power down setting While this bit set to 1, MPWDN pin (pin 116) will be active to force modem chip into power down mode. As for MPWDN is active high or active low. Please refer section 2.7 Power on configuration setup signal cross-reference table ...
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... AX88790 L 4.3 MAC Core Registers All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS (Page Select) in the Command Register. PAGE 0 (PS1=0,PS0=0) OFFSET 00H Command Register ( CR ) 01H Page Start Register ( PSTART ) 02H Page Stop Register ( PSTOP ) ...
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... AX88790 L PAGE 1 (PS1=0,PS0=1) OFFSET 00H Command Register ( CR ) 01H Physical Address Register 0 ( PARA0 ) 02H Physical Address Register 1 ( PARA1 ) 03H Physical Address Register 2 ( PARA2 ) 04H Physical Address Register 3 ( PARA3 ) 05H Physical Address Register 4 ( PARA4 ) 06H Physical Address Register 5 ( PARA5 ) 07H Current Page Register ...
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... Interrupt Status Register (ISR) Offset 07H (Read/Write) FIELD NAME 7 RST Reset Status : Set when AX88790 enters reset state and cleared when a start command is issued to the CR. Writing to this bit is no effect. 6 RDC Remote DMA Complete Set when remote DMA operation has been completed ...
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... AX88790 L 4.3.3 Interrupt mask register (IMR) Offset 0FH (Write) FIELD NAME 7 - Reserved 6 RDCE DMA Complete Interrupt Enable. Default “low” disabled. 5 CNTE Counter Overflow Interrupt Enable. Default “low” disabled. 4 OVWE Overwrite Interrupt Enable. Default “low” disabled. 3 TXEE Transmit Error Interrupt Enable. Default “low” disabled. ...
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... FIELD NAME 7 OWC Out of window collision 6:4 - Reserved 3 ABT Transmit Aborted Indicates the AX88790 aborted transmission because of excessive collision. 2 COL Transmit Collided Indicates that the transmission collided at least once with another station on the network Reserved 0 PTX Packet Transmitted Indicates transmission without error. ...
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... AX88790 L 4.3.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write) FIELD NAME 7 - Reserved 6:0 IFG Inter-frame Gap Segment 1. Default value 0cH. 4.3.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write) FIELD NAME 7 - Reserved 6:0 IFG Inter-frame Gap Segment 2. Default value 12H. 4.3.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write) ...
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... AX88790 L 4.3.15 General Purpose Input Register (GPI) Offset 17H (Read) FIELD NAME 7 - Reserved 6 GPI2 This register reflects GPI[2] input value. May connect to external PHY speed status. 5 GPI1 This register reflects GPI[1] input value. May connect to external PHY duplex status. 4 GPI0 This register reflects GPI[0] input value. May connect to external PHY link status. ...
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... AX88790 L 4.4 The Embedded PHY Registers The MII management 16-bit register set implemented is as follows. And the following sub-section will describes each field of the registers. The format for the “FIELD” descriptions is as follows: the first number is the register number, the second number is the bit position in the register and the name of the instantiated pad is in capital letters. The format for the “ ...
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... AX88790 L 4.4.1 MR0 -- Control Register Bit Descriptions FIELD TYPE 0.15 (SW_RESET) R/W 0.14 (LOOPBACK) R/W 0.13(SPEED100) R/W 0.12 (NWAY_ENA) R/W 0.11 (PWRDN) R/W 0.10 (ISOLATE) R/W 0.9 (REDONWAY) R/W 0.8 (FULL_DUP) R/W 0.7 (COLTST) R/W 0.6:0 (RESERVED) NA 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION Reset. Setting this bit will reset the PHY. All registers will be set to their default state. This bit is self-clearing. The default is 0. ...
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... AX88790 L 4.4.2 MR1 -- Status Register Bit Descriptions FIELD TYPE 1.15 (T4ABLE) R 1.14 (TXFULDUP) R 1.13 (TXHAFDUP) R 1.12 (ENFULDUP) R 1.11 (ENHAFDUP) R 1.10:7 (RESERVED) R 1.6 (NO_PA_OK) R 1.5 (NWAYDONE) R 1.4 (REM_FLT) R 1.3 (NWAYABLE) R 1.2 (LSTAT_OK) R 1.1 (JABBER) R 1.0 (EXT_ABLE) R 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION 100Base-T4 Ability. This bit will always Not able. 1: Able. 100Base-TX Full-Duplex Ability. This bit will always ...
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... AX88790 L 4.4.3 MR2, MR3 -- Identification Registers (1 and 2) Bit Descriptions FIELD TYPE 2.15:0 (OUI[3:18]) R 3.15:10 (OUI[19:24]) R 3.9:4 (MODEL[5:0]) R 3.3:0 (VERSION[3:0]) R 4.4.4 MR4 – Autonegotiation Advertisement Registers Bit Descriptions FIELD TYPE 4.15 (NEXT_PAGE) R/W 4.14 (ACK) R/W 4.13 (REM_FAULT) R/W 4.12:10 (PAUSE) R/W 4.9 (100BASET4) R/W 4.8 (100BASET_FD) R/W 4.7 (100BASETX) R/W 4.6 (10BASET_FD) R/W 4.5 (10BASET) R/W 4.4:0 (SELECT) R/W 4.4.5 MR5 – Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions ...
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... AX88790 L 4.4.6 MR5 –Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Descriptions FIELD TYPE 5.15 R (LP_NEXT_PAGE) 5.14 (LP_ACK) R 5.13 R (LP__MES_PAGE) 5.12 (LP_ACK2) R 5.11 (LP_TOGGLE) R 5.10:0 (MCF) R 4.4.7 MR6 – Autonegotiation Expansion Register Bit Descriptions FIELD TYPE 6.15:5 (RESERVED) R 6.4 R/LH (PAR_DET_FAULT) 6.3 R (LP_NEXT_PAGE_AB LE) 6.2 R (NEXT_PAGE_ABLE) 6.1 (PAGE_REC) R/LH 6.0 R (LP_NWAY_ABLE) 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION Next Page ...
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... AX88790 L 4.4.8 MR7 –Next Page Transmit Register Bit Descriptions FIELD TYPE 7.15 (NEXT_PAGE) R/W 7.14 (ACK) R 7.13 (MESSAGE) R/W 7.12 (ACK2) R/W 7.11 (TOGGLE) R 7.10:0 (MCF) R/W 4.4.9 MR16 – PCS Control Register Bit Descriptions FIELD TYPE 16.15 (LOCKED) R 16.14-12 (UNUSED) R 16.11-4 (TESTBITS) R/W 16.3 (LOOPBACK) R/W 16.2 (SCAN) R/W 16.1 (FORCE R/W LOOPBACK) 16.0 (SPEEDUP R/W COUNTERS) 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION Next Page. This bit indicates whether or not this is the last next page to be transmitted ...
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... AX88790 L 4.4.10 MR17 –Autonegotiation Register A Bit Descriptions FIELD TYPE 17.15-13 R 17.12 R 17.11 R 17.10 R 17.9 R 17.8 R 17.7 R 17.6 R 17.5 R 17.4 R 17.3 R 17.2 R 17.1 R 17.0 R 4.4.11 MR18 –Autonegotiation Register B Bit Descriptions FIELD TYPE 18.15 R 18.14 R 18.13 R 18.12 R 18.11 R 18.10 R 18.9 R 18.8 R 18.7 R 18.6 R 18.5 R 18.4 R 18.3 R 18.2 R 18.1 R 18.0 R 4.4.12 MR20 –User Defined Register Bit Descriptions FIELD TYPE 20.[15:0] R/W 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION Reserved ...
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... AX88790 L 4.4.13 MR21 –RXER Counter Register Bit Descriptions FIELD TYPE 21.0 W 21.15:0 R 21.7:0 R 21.11:8 R 21.15:12 R 4.4.14 MR28 –Device-Specific Register 1 (Status Register) Bit Descriptions FIELD TYPE 28.15:9 (UNUSED) R 28.8 (BAD_FRM) R/LH 28.7 (CODE) R/LH 28.6 (APS) R 28.5 (DISCON) R/LH 28.4 (UNLOCKED) R/LH 28.3 (RXERR_ST) R/LH 28.2 (FRC_JAM) R/LH 28.1 (LNK100UP) R 28.0 (LNK10UP) R 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION This bit, when 0 puts this register in 16-bit counter mode. When 1, it puts this register in 8-bit counter mode ...
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... AX88790 L 4.4.15 MR29 –Device-Specific Register 2 (100Mbps Control) Bit Descriptions FIELD TYPE 29.15 (LOCALRST) R/W 29.14 (RST1) R/W 29.13 (RST2) R/W 29.12 (100_OFF) R/W 29.11 (LED_BLINK) R/W 29.10 (CRS_SEL) R/W 29.9 (LINK_ERR) R/W 29.8 (PKT_ERR) R/W 29.7 (PULSE_STR) R/W 29.6 (EDB) R/W 29.5 (SAB) R/W 29.4 (SDB) R/W 29.3 (CARIN_EN) R/W 29.2 (JAM_COL) R/W 29.1 (FEF-EN) R/W 29.0 (FX) R/W 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION Management Reset. This is the local management reset bit. Writing logic 1 to this bit will cause the lower 16 registers and registers 28 and reset to their default values ...
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... AX88790 L 4.4.16 MR30 –Device-Specific Register 3 (10Mbps Control) Bit Descriptions FIELD TYPE 30.15 (Test10TX) R/W 30.14 (RxPLLEn) R/W 30.13 (JAB_DIS) R/W 30.12:7 (UNUSED) R/W 30.6 (LITF_ENH) R/W 30.5 (HBT_EN) R/W 30.4 (ELL_EN) R/W 30.3 (APF_EN) R/W 30.2 (RESERVED) R/W 30.1 (SERIAL _SEL) R/W 30.0 (ENA_NO_LP) R/W 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION When high and 10Base-T is powered up, a continuous 10 MHz signal (1111) will be transmitted. This is only meant for testing. Default 0. ...
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... AX88790 L 4.4.17 MR31 –Device-Specific Register 4 (Quick Status) Bit Descriptions FIELD TYPE 31.15 (ERROR) R 31.14 R (RXERR_ST)/(LINK_ST AT_CHANGE) 31.13 (REM_FLT) R 31.12 R (UNLOCKED)/(JABBE R) 31.11 (LSTAT_OK) R 31.10 (PAUSE) R 31.9 (SPEED100) R 31.8 (FULL_DUP) R 31.7 (INT_CONF) R/W 31.6 (INT_MASK) R/W 31.5:3 R (LOW_AUTO__STATE) 31.2:0 R (HI_AUTO_STATE) 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION Receiver Error. When this bit indicates that a receive error has been detected ...
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... AX88790 L 5.0 Device Access Functions 5.1 PCMCIA interface access functions. 5.1.1 Attribute Memory access function functions. Attribute Memory Read function Function Mode REG# Standby Mode X Byte Access (8 bits Word Access (16 bits) L Odd Byte Only Access L Attribute Memory Write function Function Mode REG# Standby Mode ...
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... AX88790 L 5.2 MII Station Management functions. Basic Operation The primary function of station management is to transfer control and status information about the PHY to a management entity. This function is accomplished by the MDC clock input from MAC entity, which has a maximum frequency of 12.5 MHz (for internal PHY only external PHY please refer to the relevant specification), along with the MDIO signal ...
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... AX88790 L 6.0 Electrical Specification and Timings 6.1 Absolute Maximum Ratings Description Operating Temperature Storage Temperature Supply Voltage Input Voltage Output Voltage Lead Temperature (soldering 10 seconds maximum) Note: Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability. ...
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... Note: Some chips may need long power down for successful PHY auto negotiation Root of cause: The PHY inside of AX88790 has a special request due to the semiconductor’s process. Namely, it needs a very long power down for successful Auto Negotiation for some chips. We made a test in lab and found it would be no problem if the PHY's initial time kept for 2 sec for all chips ...
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... AX88790 L 3. Set the PHY register MR0 with 0x1200h(0001,0010,0000,0000) -- bit 12,9 of MR0 to '1' (auto negotiation enable and restart auto negotiation) 3-in-1 PCMCIA Fast Ethernet Controller 42 ASIX ELECTRONICS CORPORATION ...
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... AX88790 L 6.4.3 Attribute Memory Read Timing A[9:0], REG# CE# Tsu(A) OE# Tv(WT-OE) WAIT# Ten(OE) D[15:0] Symbol Description TcR READ CYCLE TIME Ta(A) ADDRESS ACCESS TIME Ta(CE) CARD ENABLE ACCESS TIME Ta(OE) OUTPUT ENABLE ACCESS TIME Tdis(OE) OUTPUT DISABLE TIME FROM OE# Ten(OE) OUTPUT ENABLE TIME FROM OE# Tv(A) DATA VALID FROM ADDRESS CHANGE ...
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... AX88790 L 6.4.4 Attribute Memory Write Timing A[9:0], REG# CE# OE# Tsu(A) WE# WAIT# Tsu(OE-WE) D[15:0](Din) D[15:0](Dout) Symbol Description TcW WRITE CYCLE TIME Tw(WE) WRITE PULSE WIDTH Tsu(A) ADDRESS SETUP TIME Tsu(A-WEH) ADDRESS SETUP TIME FOR WE# Tsu(CE-WEH) CARD ENABLE SETUP TIME FOR WE# Tsu(D-WEH) DATA SETUP TIME FOR WE# ...
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... AX88790 L 6.4.5 I/O Read Timing A[9:0] REG# CE# IORD# TsuA INPACK# IOIS16# TdfIOIS16 WAIT# D[15:0] Symbol Description Td DATA DELAY AFTER IORD# Th DATA HOLD FOLLOWING IORD# Tw IORD# WIDTH TIME TsuA ADDRESS SETUP BEFORE IORD# ThA ADDRESS HOLD BEFORE IORD# TsuCE CE# SETUP BEFORE IORD# ThCE CE# HOLD BEFORE IORD# ...
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... AX88790 L 6.4.6 I/O Write Timing A[9:0] REG# CE# IOWR# TsuA IOIS16# TdfIOIS16 WAIT# D[15:0] Symbol Description Tsu DATA SETUP BEFORE IOWR# Th DATA HOLD FOLLOWING IOWR# Tw IOWR# WIDTH TIME TsuA ADDRESS SETUP BEFORE IOWR# ThA ADDRESS HOLD BEFORE IOWR# TsuCE CE# SETUP BEFORE IOWR# ThCE CE# HOLD BEFORE IOWR# ...
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... AX88790 L 6.4.7 MII Timing TXCLK TXD<3:0> TXEN RXCLK RXD<3:0> RXDV RXER Symbol Description Ttclk Cycle time(100Mbps) Ttclk Cycle time(10Mbps) Ttch high time(100Mbps) Ttch high time(10Mbps) Trch low time(100Mbps) Trch low time(10Mbps) Ttv Clock to data valid Tth Data output hold time Trclk Cycle time(100Mbps) ...
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... AX88790 L 7.0 Package Information pin 1 b SYMBOL 3-in-1 PCMCIA Fast Ethernet Controller MILIMETER MIN. NOM 0.05 0.1 1.35 1.40 0.17 0.22 13.90 14.00 19.90 20.00 0.5 15.60 16.00 21.00 22.00 0.45 0.60 1.00 0° 48 ASIX ELECTRONICS CORPORATION MAX 0.15 1.45 1.6 0.27 14.10 20.10 16.40 23.00 0.75 7° ...
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... AX88790 L Appendix A: Application Note 1 A.1 Using Crystal 25MHz AX88790 XTALIN 25MHz Crystal 33pf Note: The capacitors (33pf) may be various depend on the specification of crystal. While designing, please refer to the suggest circuit provided by crystal supplier. A.2 Using Oscillator 25MHz AX88790 XTALIN 3.3V Power OSC 25MHz 3-in-1 PCMCIA Fast Ethernet Controller ...
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... Appendix B: Power Consumption Reference Data The following reference data of power consumption are measured base on prime application, that is AX88790 + EEPROM + 74LV04, at 3.3V/25 °C room temperature. Note: 74LV04 is used for LEDs buffer or driver. Designer may omit the part and drive LED directly by AX88790. Item 1 Power save mode ( Power Down register bit set to “ ...
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... AX88790 L Errata of AX88790 1. MII Station Management functions have some differences from previous target specification. Description: The target specification is using station management can access both internal PHY registers and external PHY registers when the PHY address is matched as describe in section 5.2. Anyway, this version can only access the current selected PHY’ ...
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... AX88790 L Demonstration Circuit (A) : AX88790 + HomePNA 1M8 PHY AX88790 10BASE-T/100BASE-TX & 1M HomePNA Application with NS83851 PHYceiver.(reference only) U4 GND 1 GND SD3 2 D3 SD4 3 D4 SD5 4 D5 SD6 5 D6 SD7 6 D7 CE1# 7 CE1# 8 A10 OE# 9 OE# 10 A11 SA9 11 A9 SA8 A13 ...
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... AX88790 L SA[0..9] U3 SD[0..15] SA0 4 CE1# SA1 5 CE1# OE# SA2 6 OE# WE# SA3 7 WE# CE2# SA4 8 CE2# IORD# SA5 9 IORD# IOWR# SA6 10 IOWR# RESET SA7 11 RESET REG# SA8 12 REG# SA9 15 IREQ# SD0 42 IREQ# IOIS16# SD1 41 IOIS16# WAIT# SD2 39 WAIT# INPACK# SD3 38 INPACK# SPKR# SD4 37 SPKR# ...
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... AX88790 L RESET# RESET# RXER RXER RXDV RXDV COL COL CRS CRS RXCK R7 20 RXCLK RXD0 TXCK RXD0 RXD1 RXD1 RXD2 RXD2 RXD3 RXD3 TXCK TXCLK TXEN R8 20 TXEN TXD0 RXCK TXD0 TXD1 TXD1 TXD2 TXD2 TXD3 TXD3 MDC R5 2K MDC MDIO MDIO 3 ...
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... AX88790 L ZVREG ZVREG TPOP TPOP TPON TPON TPIP TPIP TPIN TPIN LNKLED LNKLED SPDLED SPDLED FULLED FULLED TIP TIP RING RING HSPDLED HSPDLED HCOLLED HCOLLED HACTLED HACTLED 3.3V 3.3V GND GND R12 0 ZVREG C2 + C17 R14 0.1u 49.9 10uF/16V TPOP TPON TPIP TPIN R28 R29 49.9 49.9 C26 C25 0 ...
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... AX88790 L J1 HACTLED 1 HCOLLED 2 HSPDLED 3 GND 4 R45 LTIP 5 R78 LRING 6 LTIP 7 LRING 8 CON8 J3 FULLED 1 LNKLED 2 SPDLED 3 GND 4 RX- 5 RX+ 6 TX- 7 TX+ 8 CON8 TX+ TX- RX+ RX- R45 R78 D1 HCOLLED J4 1 LED TIP 4 HACTLED RING LED NC RJ11-S D4 HSPDLED LED D2 FULLED J2 1 LED ...
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... AX88790 L Demonstration Circuit (B) : AX88790 Only AX88790 10BASE-T/100BASE-TX Application. (reference only) U4 GND 1 GND SD3 2 D3 SD4 3 D4 SD5 4 D5 SD6 5 D6 SD7 6 D7 CE1# 7 CE1# 8 A10 OE# 9 OE# 10 A11 SA9 11 A9 SA8 A13 14 A14 WE# 15 WE# IREQ# 16 IREQ# VDD 17 VCC 18 VPP1 ...
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... AX88790 L SA[0..9] U3 SD[0..15] SA0 4 CE1# SA1 5 CE1# OE# SA2 6 OE# WE# SA3 7 WE# CE2# SA4 8 CE2# IORD# SA5 9 IORD# IOWR# SA6 10 IOWR# RESET SA7 11 RESET REG# SA8 12 REG# SA9 15 IREQ# SD0 42 IREQ# IOIS16# SD1 41 IOIS16# WAIT# SD2 39 WAIT# INPACK# SD3 38 INPACK# SPKR# SD4 37 SPKR# ...
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... AX88790 L ZVREG ZVREG TPOP TPOP TPON TPON TPIP TPIP TPIN TPIN LNKLED LNKLED SPDLED SPDLED FULLED FULLED *5 R41 : LED Low Activity be used. 3.3V_Out R41 0 3.3V GND GND ZVREG C2 + C17 R14 0.1u 49.9 10uF/16V TPOP TPON TPIP TPIN R28 R29 49.9 49.9 C26 C25 0.1u 0.001u 3-in-1 PCMCIA Fast Ethernet Controller ...
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... AX88790 GND 4 R45 5 R78 CON8 TX+ J3 TX- FULLED 1 LNKLED RX+ 2 SPDLED RX- 3 GND 4 RX- R45 5 RX+ 6 TX- 7 R78 TX+ 8 CON8 3-in-1 PCMCIA Fast Ethernet Controller D2 FULLED J2 1 LED LNKLED 6 LED SPDLED 7 8 LED RJ45N Title Size A4 Date ...