24llc16 Ceramate Technical Co., Ltd., 24llc16 Datasheet
24llc16
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24llc16 Summary of contents
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... Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load bytes of data into the EEPROM in a single write operation. Another significant feature of the 24LLC1616 is its support for fast mode and standard mode. ...
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... SDA Start/Stop Logic WP SCL Slave Address Comparator Figure 5-1. 24LLC16 Block Diagram * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Tel:886-3-3214525 Fax:886-3-3521052 LC16 16K-Bit-Serial EEPROM Control Logic Word Address Row ...
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... NOTE: Table 5-1. 24LLC16 Pin Descriptions Name Type A0, A1, A2 – No internal connection V – Ground pin. SS SDA I/O Bi-directional data pin for the I trigger input and open-drain output. An external pull-up resistor must be connected to V SCL Input Schmitt trigger input pin for serial clock input. ...
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WP Figure 5-3. Pin Circuit Type 1 SDA * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Tel:886-3-3214525 Fax:886-3-3521052 16K-Bit-Serial EEPROM SCL Figure 5-4. Pin Circuit ...
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... The bus is controlled by a master device which generates the serial clock and start/stop conditions, controlling bus access. Only one 24LLC16 devices can be connected to the I 6). Both the master and slaves can operate as a transmitter or a receiver, but the master device determines which bus operating mode would be active ...
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I C-BUS PROTOCOLS 2 Here are several rules for I C-bus transfers: — A new data transfer can be initiated only when the bus is currently not busy. — MSB is always transferred first in transmitting data. — During ...
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... The most significant four bits of the slave address are called the “device identifier.” The identifier for the 24LLC16 is “1010B”. The next three bits (B2, B1, B0) are for block selection. They are used by the master to select which of the blocks of internal memory (1 block=256 words) are to be accessed. (see Table 5-2 below ...
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... Following a start condition, the master sends the device identifier (4 bits), three “don’t care” bits, and an R/ set to “0” onto the bus. Then the addressed 24LLC16 generates an ACK, and waits for the next byte. The next byte to be transmitted by the master is the word address. This 8-bit address is written into the word address ...
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... PAGE WRITE OPERATION The 24LLC16 can also perform 16-byte page write operation. A page write operation is initiated in the same way as a byte write operation. However, instead of finishing the write operation after the first data byte is transferred, the master can transmit additional bytes. The 24LLC166 responds with an ACK each time it receives a complete byte of data (see Figure 5-10) ...
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... POLLING FOR AN ACK SIGNAL When the master issues a stop condition to initiate a write cycle, the 24LLC16 starts an internal write cycle. The master can then immediately begin polling for an ACK from the slave device to determine whether the write cycle is completed. To poll for an ACK signal in a write operation, the master issues a start condition followed by the slave address. ...
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... HARDWARE-BASED WRITE PROTECTION You can also write-protect the entire memory area of the 24LLC16 This method of write protection is controlled by the state of the Write Protect (WP) pin. When the WP pin is connected to V The 24LLC16 will acknowledge slave and word address, but it will not generate an acknowledge after receiving first byte of data ...
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... When the master receives an ACK for the word address, it immediately re-issues a start condition followed by another slave address, with the R/ 3. The 24LLC16 then sends an ACK and the 8-bit data stored at the pointed address this point, the master does not acknowledge the transmission, generating a stop condition. ...
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... EEPROM to be read sequentially in a single operation. After the entire EEPROM is read, the word address pointer “rolls over” and the 24LLC16 continues to transmit data for each ACK it receives from the master (see Figure 5-14). ...
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ELECTRICAL DATA ( Parameter Symbol V Supply voltage CC V Input voltage IN V Output voltage T Operating temperature T Storage temperature STG V Electrostatic discharge ESD Table 5-4. D.C. Electrical Characteristics (T = – 25 ...
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... Upon customers request 400 kHz (Max.) in standard mode and 1 MHz in fast mode are available. 2. When acting as a transmitter, the 24LLC16 must provide an internal minimum delay time to bridge the undefined period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a start or stop condition ...
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F SCL t SU:STA SDA In SDA Out Figure 5-15. Timing Diagram for Bus Operations SCL SDA 8th Bit ACK WORDn Figure 5-16. Write Cycle Timing Diagram * All specs and applications shown above subject to change without prior ...
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CHARACTERISTIC CURVES The characteristic values shown in the following graphs are based on actual test measurements. They do not, however, represent guaranteed operating values. (Frequency = 100 kHz) 2.0 1.6 1.2 I (mA) CC 0.8 0.4 0 1.5 * All ...
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I (uA 1.5 (Frequency = 100 kHz) 1.5 1.2 0.9 I (uA) CC 0.6 0.3 0 1.5 * All specs and applications shown above subject to change ...
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(mA All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, ...
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Package Information (1) PDIP-8L PIN #1 INDENT O0.025 DEEP 0.006-0.008 7 (4X DIMENSIONS IN MILLIMETERS SYMBOL MIN 0.38 A2 3.25 B 0.36 B1 1.14 B2 0.81 0. 9.12 E 7.62 6. ...
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SOP-8L(JEDEC (4X) e DIMENSIONS IN MILLIMETERS SYMBOL MIN A 1. 0.33 C 0.19 D 4.80 3. 5.79 0. £ All specs and ...
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TSSOP-8L PIN 1 INDICATOR O0.70 SURFACE POLISHED SYMBOLS MIN A 1. 2.90 E 6. 0. £ All specs ...