vt82c586a

Manufacturer Part Numbervt82c586a
DescriptionIntegrated Peripheral Controller
ManufacturerETC-unknow
vt82c586a datasheet
 


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vt82c586a Summary of contents

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    ...

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    ‹ 86$ 2IILFH 7DLSHL 2IILFH ...

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    ... Document Release Date Preliminary Release 10/13/96 Preliminary Revision 0.1 October 13, 1996 R H EVISION ISTORY Revision Initial release -i- VT82C586A Initials Revision History ...

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    ... IDE I/O Registers.................................................................................................................................................................................. 33 Universal Serial Bus Controller Registers (Function 2) .................................................................................................... 34 PCI Configuration Space Header .......................................................................................................................................................... 34 USB-Specific Configuration Registers.................................................................................................................................................. 35 USB I/O Registers................................................................................................................................................................................. 35 ELECTRICAL SPECIFICATIONS............................................................................................................................................... BSOLUTE AXIMUM ATINGS DC C ................................................................................................................................................................ 36 HARACTERISTICS PACKAGE MECHANICAL SPECIFICATIONS ........................................................................................................................ 37 Preliminary Revision 0.1 October 13, 1996 T C ABLE OF ONTENTS ................................................................................................................................................. 36 -ii- VT82C586A Table of Contents ...

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    ... FIGURE 1. PIN DIAGRAM............................................................................................................................................................. 4 FIGURE 2. STRAP OPTION CIRCUIT....................................................................................................................................... 28 FIGURE 3. MECHANICAL SPECIFICATIONS - 208-PIN PLASTIC FLAT PACKAGE.................................................... 37 Preliminary Revision 0.1 October 13, 1996 L F IST OF IGURES -iii- VT82C586A List of Figures ...

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    ... TABLE 1. PIN DESCRIPTIONS..................................................................................................................................................... 5 TABLE 2. SYSTEM I/O MAP ....................................................................................................... ................................................ 10 TABLE 3. REGISTERS.................................................................................................................................................................. 10 TABLE 4. KEYBOARD CONTROLLER COMMAND CODES .............................................................................................. 18 Preliminary Revision 0.1 October 13, 1996 L T IST OF ABLES -iv- VT82C586A List of Tables ...

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    ... USB v.1.0 and Intel Universal HCI v.1.1 compatible Eighteen level (doublewords) data FIFO with full scatter and gather capability Root hub and two function ports with integrated physical layer transceivers Legacy keyboard and PS/2 mouse support Preliminary Revision 0.1 October 13, 1996 VT82C586A PIPC P NTEGRATED ERIPHERAL PCI- ...

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    ... Dual interrupt and DMA channel controllers for on-board plug and play devices Microsoft Windows 95 Built-in Nand-tree pin scan test capability 0.5um mixed voltage, high speed and low power CMOS process Single chip 208 pin PQFP Preliminary Revision 0.1 October 13, 1996 TM and plug and play BIOS compliant -2- VT82C586A 2 C capabilities Features ...

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    ... The IDE controller is SFF-8038i v1.0 and Microsoft Windows-95 compliant. b) Universal Serial Bus controller that is USB v1.0 and Universal HCI v1.1 compliant. The VT82C586A includes the root hub with two function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous peripherals to be inserted into the system with universal driver support ...

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    ... Preliminary Revision 0.1 October 13, 1996 P INOUTS Figure 1. Pin Diagram Note: Pin names in parentheses (...) indicate alternate function -4- VT82C586A (IRQ8 ...

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    ... Reset and Clock I Power Good. Connected to the POWERGOOD signal on the Power Supply. O PCI Reset. An active low reset signal for the PCI bus. The VT82C586A will generate PCIRST# during power-up or from the control register. O Reset Drive. RSTDRV is the reset signal to the ISA bus. ...

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    ... ISA data bus. O Bus Address Latch Enable. BALE is an active high signal asserted by the VT82C586A to indicate that the address (SA[19:0], LA[23:17] and the SBHE# signal) is valid I 16-Bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to indicate that they support 16-bit I/O bus cycles ...

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    ... KBRC# MSCK / IRQ1 110 Preliminary Revision 0.1 October 13, 1996 O Terminal Count. The VT82C586A asserts TC to DMA slaves as a terminal count indicator. I Interrupt Request. The IRQ signals provide both system board components and ISA Bus I/O devices with a mechanism for asynchronously interrupting the CPU. ...

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    ... DACKn by external 137, DACK0 as DACEN, DACK1-3,5-7 as EXTSMI2-7 1: DACKn as DACKn O General Purpose Write Enable 1. LATCH enable signal to an external 373 for general purpose outputs (SD15-8). Miscellaneous Control I External SMI. External input to trigger SMI output to the CPU. I External IOAPIC Chip Select. -8- VT82C586A Pinouts ...

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    ... Preliminary Revision 0.1 October 13, 1996 Power and Ground I Power Supply. 4.5 to 5.5V. I Power Supply. For the CPU Voltage. I PCI Voltage. 3 USB Differential Output Power Source I USB Differential Output Ground I Ground -9- VT82C586A Pinouts ...

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    ... R EGISTERS Register Overview The following tables summarize the configuration and I/O registers of the VT82C586A. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), “—” for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1’ ...

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    ... Write Single Mask D6 Write Mode Default Acc D8 Clear Byte Pointer FF — Master Clear — Clear Mask — Read / Write Mask — RW Default Acc — RW — RW — RW -11- VT82C586A Default Acc Register Overview ...

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    ... — — 0300 RW Default Acc — -12- VT82C586A Default Acc — — 0000 RW 0000 † ...

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    ... RO 0 Primary Channel Command -reserved- 2 Primary Channel Status 3 -reserved- 4-7 Primary Channel PRD Table Addr 8 Secondary Channel Command 9 -reserved- A Secondary Channel Status B -reserved- C-F Secondary Channel PRD Table Addr -13- VT82C586A Default Acc A8A8A8A8 ...

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    ... Port 2 Status / Control — 00000301 RW 00 — — Default Acc — — 2000 RW 00 — -14- VT82C586A Default Acc 0000 RW 0000 WC 0000 RW 0000 RW 00000000 0080 WC 0080 WC Register Overview ...

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    ... Register Number Used to select a specific DWORD in the device’s configuration space 1-0 Fixed ........................................ always reads 0 Port CFF-CFC - Configuration Data .............................. RW Refer to PCI Bus Specification Version 2.1 for further details on operation of the above configuration registers. Preliminary Revision 0.1 October 13, 1996 -15- VT82C586A Configuration Space I/O ...

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    ... A20 Address Line Enable 0 A20 disabled / forced 0 (real mode) ...... default 1 A20 address line enabled 0 High Speed Reset 0 Normal 1 Briefly pulse system reset to switch from protected mode to real mode -16- VT82C586A Detailed descriptions of the (duplication of that Bit-3 should be cleared to Register Descriptions ...

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    ... System Flag ................................................ default=0 – – This bit may be read back as status register bit-2 1 Mouse Interrupt Enable 0 Keyboard Interrupt Enable -17- VT82C586A 0 Keyboard Output Buffer Empty............. default 1 Keyboard Output Buffer Full 0 Input Buffer Empty................................ default 1 Input Buffer Full 0 Power-On Default .................................. default 1 ...

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    ... Port 64 - Keyboard / Mouse Command .......................... WO This port is used to send commands to the keyboard / mouse controller. The command codes recognized by the VT82C586A are listed n the table below. Note: The VT82C586A Keyboard Controller is compatible with the VIA VT82C42 Industry-Standard Controller except that due to its integrated nature, many of the ...

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    ... Channel 3 DMA Page (M-3).........RW 0000 0000 1000 1111 Channel 4 DMA Page (S-0) ..........RW 0000 0000 1000 1011 Channel 5 DMA Page (S-1) ..........RW 0000 0000 1000 1001 Channel 6 DMA Page (S-2) ..........RW 0000 0000 1000 1010 Channel 7 DMA Page (S-3) .........RW -19- VT82C586A ...

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    ... Reserved 4-0 T7-T3 of Interrupt Vector Address Port A0 - Slave Interrupt Control Shadow ..................... RO ........................................ always reads 0 7-5 Reserved 4 OCW3 bit OCW2 bit 7 2 ICW4 bit ICW4 bit 1 0 ICW1 bit 3 Port A1 - Slave Interrupt Mask Shadow ........................ RO 7-5 Reserved ........................................ always reads 0 4-0 T7-T3 of Interrupt Vector Address -20- VT82C586A Register Descriptions ...

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    ... The system Real Time Clock (RTC) is part of the “CMOS” block. located at specific offsets in the CMOS data area. Detailed descriptions of CMOS / RTC operation and programming can be obtained from the VIA VT82887 Data Book or numerous other industry publications. -21- VT82C586A The RTC control registers are Register Descriptions ...

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    ... PCI to ISA Bridge Registers (Function 0) All registers are located in the function 0 PCI configuration space of the VT82C586A. These registers are accessed through PCI configuration mechanism #1 via I/O address CF8/CFC. PCI Configuration Space Header Offset 1-0 - Vendor ID = 1106h ......................................... RO Offset 3-2 - Device ID = 0586h .......................................... RO Offset 5-4 - Command ....................................................... RW 15-4 Reserved ........................................ always reads 0 3 Special Cycle Enable ...

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    ... Integrated USB Controller Disable 0 Enable .................................................... default 1 Disable 1 Integrated IDE Controller Disable 0 Enable .................................................... default 1 Disable 0 512K PCI Memory Decode 0 Use the contents of bits 15-12 of Rx4Eh as the top of PCI memory 1 Use the contents of bits 15-12 of Rx4Eh plus 512K as the top of PCI memory ............ default -23- VT82C586A ............... default Register Descriptions ...

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    ... Forward D8000-DBFFF Accesses to PCI ......def=0 5 Forward D4000-D7FFF Accesses to PCI .......def=0 4 Forward D0000-D3FFF Accesses to PCI .......def=0 3 Forward CC000-CFFFF Accesses to PCI .....def=0 Forward C8000-CBFFF Accesses to PCI ......def Forward C4000-C7FFF Accesses to PCI .......def=0 Forward C0000-C3FFF Accesses to PCI .......def=0 0 -24- VT82C586A .................................................... default Register Descriptions ...

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    ... MIRQ0 Routing (same as PIRQD# routing) ....def=0 Offset 56 - PNP IRQ Routing 2 ....................................... RW 7-4 PIRQA# Routing (same as PIRQD# routing) ...def=0 3-0 PIRQB# Routing (same as PIRQD# routing) ...def=0 Offset 57 - PNP IRQ Routing 3 ....................................... RW PIRQC# Routing (same as PIRQD# routing) ...def=0 7-4 3-0 MIRQ1 Routing (same as PIRQD# routing) ....def=0 -25- VT82C586A Register Descriptions ...

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    ... Power Management Refer to VIA application note AP-053 (“APM-Compliant Power Management Model of the VT82C586A”) for additional information on power mangement programming. Offset 80 - Primary Activity Detect Enable .................... RW 7 Keyboard Controller Access Detect Enable 0 Disable ...................................................default 1 Enable activity detect status bit to be set by access to I/O port 60h ...

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    ... Suspend Mode Enable 0 Normal Operating Mode........................ default 1 Put CPU into Suspend Mode 1 Reserved (do not program) .......................default=0 0 Global SMI Enable ....................................default=0 Offset 8E - STPCLK# Duty Cycle ................................... RW 7-4 Reserved ........................................ always reads 0 3-0 STPCLK# Duty Cycle 0000 Disable................................................... default 0001 1/16 0010 2/16 0011 3/16 ... ... 1111 15/16 -27- VT82C586A Register Descriptions ...

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    ... Note: External strap option values may be set by connecting the indicated external pin to a 4.7K ohm pullup (for 1) or drive it low during reset with a 7407 TTL open collector buffer (for 0) as shown in the suggested circuit below: Figure 2. Strap Option Circuit -28- VT82C586A Register Descriptions ...

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    ... PCI configuration registers and Bus Master IDE I/O registers. The PCI configuration registers are located in the function 1 PCI configuration space of the VT82C586A. The Bus Master IDE I/O registers are defined in the SFF8038i v1.0 specification. PCI Configuration Space Header Offset 1-0 - Vendor ID (1106h=VIA) ................................ RO Offset 3-2 - Device ID (0571h=IDE Controller) ...

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    ... Fixed at 0001b .................................................. fixed Preliminary Revision 0.1 October 13, 1996 Offset 3C - Interrupt Line (0Eh) ..................................... RW Offset 3D - Interrupt Pin (00h) ......................................... RO 7-0 Interrupt Routing Mode 00h Legacy mode interrupt routing............... default 01h Native mode interrupt routing Offset 3E - Min Gnt (00h) ................................................. RO Offset 3F - Max Latency (00h).......................................... RO -30- VT82C586A Register Descriptions ...

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    ... Default=0 (disabled) 3-2 Reserved ........................................ always reads 0 1-0 Max DRDY Pulse Width Maximum DRDY# pulse width after the cycle count. Command will deassert in spite of DRDY# status to avoid system ready hang limitation.......................................... default 01 64 PCI clocks 10 128 PCI clocks 11 192 PCI clocks -31- VT82C586A Register Descriptions ...

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    ... Each byte defines UltraDMA33 operation for the indicated drive. The bit definitions are the same within each byte. Offset 61-60 - Primary Sector Size .................................. RW ........................................ always reads 0 15-12 Reserved 11-0 Number of Bytes Per Sector ................ default=200h Offset 69-68 - Secondary Sector Size .............................. RW 15-12 Reserved ........................................ always reads 0 11-0 Number of Bytes Per Sector ................ default=200h -32- VT82C586A Register Descriptions ...

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    ... Refer to the SFF 8038I v1.0 specification for further details. Offset 0 - Primary Channel Command Offset 2 - Primary Channel Status Offset 4-7 - Primary Channel PRD Table Address Offset 8 - Secondary Channel Command Offset A - Secondary Channel Status Offset C-F - Secondary Channel PRD Table Address Preliminary Revision 0.1 October 13, 1996 -33- VT82C586A Register Descriptions ...

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    ... There are two sets of software accessible registers: PCI configuration registers and USB I/O registers. The PCI configuration registers are located in the function 2 PCI configuration space of the VT82C586A. The USB I/O registers are defined in the UHCI v1.1 specification. PCI Configuration Space Header Offset 1-0 - Vendor ID ....................................................... RO Vendor ID ...

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    ... These registers are compliant with the UHCI v1.1 standard. Refer to the UHCI v1.1 specification for further details. Offset 1-0 - USB Command Offset 3-2 - USB Status Offset 5-4 - USB Interrupt Enable Offset 7-6 - Frame Number Offset B-8 - Frame List Base Address Offset 0C - Start Of Frame Modify Offset 11-10 - Port 1 Status / Control Offset 13-12 - Port 2 Status / Control -35- VT82C586A Register Descriptions ...

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    ... Tristate leakage current OZ I Power supply current CC Preliminary Revision 0.1 October 13, 1996 E S LECTRICAL PECIFICATIONS Min 0 -55 -0.5 = 5V) -0 3.1 - 3.6V) -0.5 DD Min Max -0.50 2 2.4 - +/-10 - +/-20 - -36- Max Unit 125 5.5 Volts 5.5 Volts V + 0.5 Volts DD Unit Condition 0.8 V +0 =4.0mA =-1.0mA OH uA 0<V < 0.45<V <V OUT Electrical Specifications VT82C586A ...

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    ... P ACKAGE 7<3   7<3 Figure 3. Mechanical Specifications - 208-Pin Plastic Flat Package Preliminary Revision 0.1 October 13, 1996 M S ECHANICAL       4 -37- PECIFICATIONS        Package Mechanical Specifications VT82C586A ...