vt82c586a ETC-unknow, vt82c586a Datasheet - Page 12

• Manufacturer Part Number: vt82c586a
• Description: Integrated Peripheral Controller
• Manufacturer: ETC-unknow

PGNT#
SA[15:0] /
DD[15:0]
SA16
LA23/DCS3B#,
LA22/DCS1B#,
LA21/DCS3A#,
LA20/DCS1A#,
LA[19:17] /
DA[2:0]
SD[15:8]
SBHE#
IOR#
IOW#
MEMR#
MEMW#
SMEMR#
SMEMW#
BALE
IOCS16#
MEMCS16#
MASTER# /
IRQ12
IOCHCK#
IOCHRDY
REFRESH#
AEN
Preliminary Revision 0.1 October 13, 1996

20-25, 27-28,
86-85, 83-80,
36-38, 40-44
63-67, 69-70
78-77
150
123
124
125
137
19
62
12
11
10
35
76
29
15
9
5
8
O
O
O
O
B
B
B
B
B
B
B
B
B
B
I
I
I
I
I
I
PCI Grant. This signal is driven by the VT82C595 to grant PCI access to the
VT82C586A.
System Address Bus/IDE Data Bus
System Address Bus
Multifunction Pins
ISA Bus Cycles:
Unlatched Address: The LA[23:17] address lines are bi-directional. These address
lines allow accesses to physical memory on the ISA bus up to 16MBytes.
PCI IDE Cycles:
Chip Select: DCS1A# is for the ATA command register block and corresponds to
CS1FX# on the primary IDE connector. DCS3A# is for the ATA command register
block and corresponds to CS3FX# on the primary IDE connector. DCS1B# is for the
ATA command register block and corresponds to CS17X# on the primary IDE
connector. DCS3B# is for the ATA command register block and corresponds to
CS37X# on the primary IDE connector.
Disk Address: DA[2:0] are used to indicate which byte in either the ATA command
block or control block is being accessed.
System Data. SD[15:8] provide the high order byte data path for devices residing on
the ISA bus.
System Byte High Enable. SBHE# indicates, when asserted, that a byte is being
transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated during
refresh cycles.
I/O Read. IOR# is the command to an ISA I/O slave device that the slave may drive
data on to the ISA data bus.
I/O Write. IOW# is the command to an ISA I/O slave device that the slave may
latch data from the ISA data bus.
Memory Read. MEMR# is the command to a memory slave that it may drive data
onto the ISA data bus.
Memory Write. MEMW# is the command to a memory slave that it may latch data
from the ISA data bus.
Standard Memory Read. SMEMR# is the command to a memory slave, under
1MB, which indicates that it may drive data onto the ISA data bus
Standard Memory Write. SMEMW# is the command to a memory slave, under
1MB, which indicates that it may latch data from the ISA data bus.
Bus Address Latch Enable. BALE is an active high signal asserted by the
VT82C586A to indicate that the address (SA[19:0], LA[23:17] and the SBHE#
signal) is valid
16-Bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to
indicate that they support 16-bit I/O bus cycles.
Memory Chip Select 16. ISA slaves that are 16-bit memory devices drive this line
low to indicate they support 16-bit memory bus cycles.
Multi-function Pin
I/O Channel Check. When this signal is asserted, it indicates that a parity or an
uncorrectable error has occurred for a device or memory on the ISA Bus.
I/O Channel Ready. Devices on the ISA Bus negate IOCHRDY to indicate that
additional time (wait states) is required to complete the cycle.
Refresh. As an output REFRESH# indicates when a refresh cycle is in progress. As
an input REFRESH# is driven by 16-bit ISA Bus masters to indicate refresh cycle.
Address Enable. AEN is asserted during DMA cycles to prevent I/O slaves from
misinterpreting DMA cycles as valid I/O cycles.
1. Rx46h[2]=1 and Rx44h[0]=0: IRQ12
2. Otherwise: MASTER#. ISA master cycle indicator
ISA Bus Control
-6-
VT82C586A
Pinouts