vt82c586a ETC-unknow, vt82c586a Datasheet - Page 13

• Manufacturer Part Number: vt82c586a
• Description: Integrated Peripheral Controller
• Manufacturer: ETC-unknow

TC
IRQ15, 14, [11:
9], [7:3]
DRQ[7:5], [3:0]
DACK[7:5],
[3:0]/
EXTSMI7-2,
DACEN
SPKR
DIORA#
DIOWA#
DIORB#
DIOWB#
DRDYA#
DRDYB#
SOE#
DDRQA
DDRQB
DDACKA#
DDACKB#
USBDATA0+
USBDATA0-
USBDATA1+
USBDATA1-
USBCLK
KBCK /
KA20G
KBDT /
KBRC#
MSCK / IRQ1
Preliminary Revision 0.1 October 13, 1996

126, 61, 71-75
128-129, 127-
31, 33, 18, 60
133, 131, 58,
132, 130, 57,
30, 7, 16, 59
134
108
109
110
32
50
51
54
55
49
89
56
45
46
47
48
95
96
97
98
99
O
O
O
O
O
O
O
O
O
B
B
B
B
B
B
B
B
I
I
I
I
I
I
I
Terminal Count. The VT82C586A asserts TC to DMA slaves as a terminal count
indicator.
Interrupt Request. The IRQ signals provide both system board components and
ISA Bus I/O devices with a mechanism for asynchronously interrupting the CPU.
DMA Request. The DREQ lines are used to request DMA services from the
VT82C586A’s DMA controller.
Multifunction Pins
Multifunction Pin
Disk I/O Read A. Primary IDE channel drive read strobe.
Disk I/O Write A. Primary IDE channel drive write strobe.
Disk I/O Read B. Secondary IDE channel drive read strobe.
Disk I/O Write B. Secondary IDE channel drive write strobe.
I/O Channel Ready A. IDE drive ready indicator.
I/O Channel Ready B. IDE drive ready indicator from the second channel (required
for UltraDMA/33 IDE interface).
System Address Transceiver Output Enable. This signal controls the output
enables of the 245 transceivers that interface the DD[15:0] signals to SA[15:0]. The
transceiver direction controls are driven by MASTER# with DD[15-0] connected to
the “A” side of the transceivers and SA[15-0] connected to the “B” side.
Disk DMA Request A. Primary IDE channel DMA request.
Disk DMA Request B. Secondary IDE channel DMA request.
Disk DMA Acknowledge A. Primary IDE channel DMA acknowledge.
Disk DMA Acknowledge B. Secondary IDE channel DMA acknowledge. This pin
is used as a power-up strap option: 0/1 = Fixed/relocatable IDE I/O address
USB Port 0 Data +
USB Port 0 Data -
USB Port 1 Data +
USB Port 1 Data -
USB Clock. Clock input for Universal serial bus interface
Multifunction Pin. Function depends on enable/disable of internal KBC.
Multifunction Pin. Function depends on enable/disable of internal KBC.
Multifunction Pin. Function depends on enable/disable of internal KBC.
Universal Serial Bus Interface
Pin 135 (ROMCS#/KBCS#) strapped 1 at power up:
Pin 135 (ROMCS#/KBCS#) strapped 0 at power up:
Normal Operation: Speaker Drive. The SPKR signal is the output of counter 2.
Power-up Strapping: 0/1 = Fixed/flexible IDE I/O base
Internal KBC enabled: Keyboard Clock. Clock to keyboard interface.
Internal KBC disabled: Gate A20: Gate A20 output from external KBC
Internal KBC enabled: Keyboard Data. Data to keyboard interface.
Internal KBC disabled: Keyboard Reset: Reset input from external KBC.
PS/2 mouse enabled: Mouse Clock. Clock to PS/2 mouse interface.
PS/2 mouse disable and internal KBC disabled: Interrupt Request 1.
IRQ 1 input from external KBC.
Normal Operation: Acknowledge. The DACK output lines indicate a request for
Power-up: Strap Inputs. Strapped inputs stored in configuration register 96h.
DMA service has been granted.
Pin 60: DACEN. To enable external 137 for decoding DACKs from XD0-2.
Other pins: External SMI or General Purpose Inputs.
Enhanced IDE Interface
Keyboard Interface
-7-
VT82C586A
Pinouts