vt82c586a ETC-unknow, vt82c586a Datasheet - Page 16

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vt82c586a

Manufacturer Part Number
vt82c586a
Description
Integrated Peripheral Controller
Manufacturer
ETC-unknow
Datasheet

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Register Overview
The following tables summarize the configuration and I/O
registers of the VT82C586A. These tables also document the
power-on default value (“Default”) and access type (“Acc”) for
each register.
(Read/Write), RO (Read/Only), “—” for reserved / used
(essentially the same as RO), and RWC (or just WC) (Read /
Write 1’s to Clear individual bits). Registers indicated as RW
may have some read/only bits that always read back a fixed
value (usually 0 if unused); registers designated as RWC or
WC may have some read-only or read write bits (see individual
register descriptions for details).
Detailed register descriptions are provided in the following
section of this document. All offset and default values are
shown in hexadecimal unless otherwise indicated
Port
00-1F
20-3F
40-5F
60-6F
(60h)
(61h)
(64h)
70-77
78-7F
80
81-8F
90-91
92
93-9F
A0-BF
A8-A9
C0-DF
E0-FF
100-CF7
CF8-CFB PCI Configuration Address 0000 1100 1111 10xx
CFC-CFF PCI Configuration Data
D00-FFFF -available for system use-
Preliminary Revision 0.1 October 13, 1996

Function
Misc Functions & Spkr Ctrl 0000 0000 0110 xxx1
KBC Command / Status
RTC/CMOS/NMI-Disable 0000 0000 0111 0nnn
-available for system use-
-available for system use-
Master DMA Controller
Master Interrupt Controller 0000 0000 001x xxxn
Timer / Counter
Keyboard Controller
KBC Data
-available for system use-
-reserved- (debug port)
DMA Page Registers
System Control
-available for system use-
Slave Interrupt Controller
VIA GPIO Ports
Slave DMA Controller
-available for system use-
Table 2. System I/O Map
Access type definitions used are RW
R
EGISTERS
Actual Port Decoding
0000 0000 0110 x0x0
0000 0000 000x nnnn
0000 0000 010x xxnn
0000 0000 0110 xnxn
0000 0000 0110 x1x0
0000 0000 1000 0000
0000 0000 1000 nnnn
0000 0000 1001 000x
0000 0000 1001 0010
0000 0000 1001 nnnn
0000 0000 101x xxxn
0000 0000 1010 100n
0000 0000 111x xxxx
0000 1100 1111 11xx
0000 0000 0111 1xxx
0000 0000 110n nnnx
-10-
Legacy I/O Registers
* RW if shadow registers are disabled
NMI Disable is port 70h (CMOS Memory Address) bit-7
RTC control occurs via specific CMOS data locations (0-0Dh)
Port Master DMA Controller Registers
Port Master Interrupt Controller Regs
Port Timer/Counter Registers
Port Keyboard Controller Registers
Port CMOS / RTC / NMI Registers
0A
0D
0B
0C
0E
00
01
02
03
04
05
06
07
08
09
0F
20
21
20
21
40
41
42
43
60
61
64
70
71
Channel 0 Base & Current Address
Channel 0 Base & Current Count
Channel 1 Base & Current Address
Channel 1 Base & Current Count
Channel 2 Base & Current Address
Channel 2 Base & Current Count
Channel 3 Base & Current Address
Channel 3 Base & Current Count
Status / Command
Write Request
Write Single Mask
Write Mode
Clear Byte Pointer FF
Master Clear
Clear Mask
Read / Write Mask
Master Interrupt Control
Master Interrupt Mask
Master Interrupt Control Shadow
Master Interrupt Mask Shadow
Timer / Counter 0 Count
Timer / Counter 1 Count
Timer / Counter 2 Count
Timer / Counter Control
Keyboard Controller Data
Misc Functions & Speaker Control
Keyboard Ctrlr Command / Status
CMOS Memory Address & NMI Disa
CMOS Memory Data (128 bytes)
Table 3. Registers
Register Overview
VT82C586A
Default Acc
Default Acc
Default Acc
Default Acc
Default Acc
WO
WO
WO
WO
WO
WO
WO
WO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
*
*

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