vt82c586a ETC-unknow, vt82c586a Datasheet - Page 28

• Manufacturer Part Number: vt82c586a
• Description: Integrated Peripheral Controller
• Manufacturer: ETC-unknow

PCI to ISA Bridge Registers (Function 0)
All registers are located in the function 0 PCI configuration
space of the VT82C586A. These registers are accessed
through PCI configuration mechanism #1 via I/O address
CF8/CFC.
PCI Configuration Space Header
Offset 1-0 - Vendor ID = 1106h ......................................... RO
Offset 3-2 - Device ID = 0586h .......................................... RO
Offset 5-4 - Command ....................................................... RW
Offset 7-6 - Status ........................................................... RWC
Offset 8 - Revision ID = nn ................................................ RO
Offset 9 - Program Interface = 00h ................................... RO
Offset A - Sub Class Code = 01h ....................................... RO
Offset B - Class Code = 06h ............................................... RO
Offset E - Header Type = 80h ............................................ RO
Offset F - BIST = 00h ......................................................... RO
Preliminary Revision 0.1 October 13, 1996
15-4 Reserved
10-9 DEVSEL# Timing .................... fixed at 01 (medium)
6-0
7-0
15
14
13
12
11
3
2
1
0
8
7
Special Cycle Enable ......................... always reads 1
Bus Master ........................................ always reads 1
Memory Space.................................... always reads 1
I/O Space
Detected Parity Error .................... write one to clear
Signalled System Error...................... always reads 0
Signalled Master Abort ..................... always reads 0
Received Target Abort .................. write one to clear
Signalled Target Abort ...................... always reads 0
Data Parity Detected.......................... always reads 0
Fast Back-to-Back.............................. always reads 0
Reserved
Header Type Code .........80h (Multifunction Device)

........................................ always reads 0
........................................ always reads 1
........................................ always reads 0
-22-
ISA Bus Control
Offset 40 - ISA Bus Control ............................................. RW
Offset 41 - Refresh and Port 92 ....................................... RW
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
ISA Command Delay
Extended ISA Bus Ready
ISA Slave Wait States
Chipset I/O Wait States
I/O Recovery Time
Extend-ALE
ROM Wait States
ROM Write
Bus Refresh Arbitration
Reserved
Port 92 Fast Reset
Reserved
Double DMA Clock
Reserved
Refresh Request Test Mode
Reserved
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Normal................................................... default
Extra
Disable................................................... default
Enable
4 Wait States.......................................... default
5 Wait States
2 Wait States.......................................... default
4 Wait States
Disable................................................... default
Enable
Disable................................................... default
Enable
1 Wait State ........................................... default
0 Wait States
Disable................................................... default
Enable
Enable .................................................... default
Disable
Disable................................................... default
Enable
Disable................................................... default
Enable
Disable................................................... default
Enable
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
Register Descriptions
VT82C586A