vt82c586a ETC-unknow, vt82c586a Datasheet - Page 29

• Manufacturer Part Number: vt82c586a
• Description: Integrated Peripheral Controller
• Manufacturer: ETC-unknow

Offset 42 - ISA Clock Control. ......................................... RW
Note: Procedure for ISA CLOCK switching:
Offset 43 - ROM Decode Control .................................... RW
Setting these bits enables the indicated address range to be
included in the ROMCS# decode:
Offset 44 - Keyboard Controller Control ........................ RW
Offset 45 - Type F DMA Control ..................................... RW
Preliminary Revision 0.1 October 13, 1996
5-4
2-0
7-1
1)
2)
3)
7
6
3
7
6
5
4
3
2
1
0
0
7
6
5
4
3
2
1
0
Latch IO16#
MCS16# Output
Reserved
ISA CLOCK Select Enable
ISA Bus Clock Select (if bit-3 = 1)
Set bit 3 to 0
Change value of bit 2-0
Set bit 3 to 1
FFFE0000h-FFFEFFFFh .......................... default=0
FFF80000h-FFFDFFFFh ......................... default=0
000E8000h-000EFFFFh ............................ default=0
000E0000h-000E7FFFh ............................ default=0
000D8000h-000DFFFFh ........................... default=0
000D0000h-000D7FFFh ............................ default=0
000C8000h-000CFFFFh ........................... default=0
000C0000h-000C7FFFh............................. default=0
Reserved
PS2 Mouse Enable
ISA Master / DMA to PCI Line Buffer .... default=0
DMA type F Timing on Channel 7 ........... default=0
DMA type F Timing on Channel 6 ........... default=0
DMA type F Timing on Channel 5 ........... default=0
DMA type F Timing on Channel 3 ........... default=0
DMA type F Timing on Channel 2 ........... default=0
DMA type F Timing on Channel 1 ........... default=0
DMA type F Timing on Channel 0 ........... default=0

000 PCICLK/3 ..............................................default
001 PCICLK/2
010 PCICLK/4
011 PCICLK/6
100 PCICLK/5
101 PCICLK/10
110 PCICLK/12
111 OSC/2
0
1
0
1
0
1
0
1
Enable.....................................................default
Disable
Disable ...................................................default
Enable
ISA Clock = PCICLK/4 .........................default
ISA Clock selected per bits 2-0
Disabled .................................................default
Enabled
........................................ always reads 0
........................................ always reads 0
-23-
Offset 46 - Miscellaneous Control 1 ................................ RW
Offset 47 - Miscellaneous Control 2 ................................ RW
Offset 48 - Miscellaneous Control 3 ................................ RW
7-3
7-3
2
1
0
7
6
5
4
3
2
1
0
2
1
0
Reserved
Pin 137 Function Control
Rx46h Rx44h
PCI Burst Read Interruptability
Post Memory Write Enable
CPU Reset Source
PCI Delay Transaction Enable
EISA 4D0/4D1 Port Enable
Interrupt Controller Shadow Register Enable
Reserved
Write Delay Transaction Time-Out Timer Enable
Read Delay Transaction Time-Out Timer Enable
Software PCI Reset ...... write 1 to generate PCI reset
Reserved
Integrated USB Controller Disable
Integrated IDE Controller Disable
512K PCI Memory Decode
bit 2
1
0
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Allow burst reads to be interrupted........ default
Don’t allow PCI burst reads to be interrupted
Disable................................................... default
Enable
Use CPURST as CPU Reset .................. default
Use INIT as CPU Reset
Disable................................................... default
Enable
Disable................................................... default
Enable
Disable................................................... default
Enable
Disable................................................... default
Enable
Disable................................................... default
Enable
Enable .................................................... default
Disable
Enable .................................................... default
Disable
Use the contents of bits 15-12 of Rx4Eh as the
top of PCI memory
Use the contents of bits 15-12 of Rx4Eh plus
512K as the top of PCI memory ............ default
bit-0
0
x
1
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
MASTER#
MASTER#
Pin 137
IRQ12
Register Descriptions
VT82C586A
............... default