vt82c586a ETC-unknow, vt82c586a Datasheet - Page 34

• Manufacturer Part Number: vt82c586a
• Description: Integrated Peripheral Controller
• Manufacturer: ETC-unknow

The following 4 registers all default to 00 at power-up (all
events disabled):
Offset 90 - ISA IRQ 7-0 as Primary Event ...................... RW
Offset 91 - ISA IRQ 15-8 as Primary Event .................... RW
Offset 92 - ISA IRQ 7-0 as Secondary Event .................. RW
Offset 93 - ISA IRQ15-8 as Secondary Event ................. RW
Offset 94 - External SMI Pin Status ................................. RO
Preliminary Revision 0.1 October 13, 1996
7-0
7-0
7-0
7-0
7
6
5
4
3
2
1
0
IRQ7-0 (1 bits enable corresponding interrupt line)
IRQ15-8 (1 bits enable corresponding interrupt line)
IRQ7-0 (1 bits enable corresponding interrupt line)
IRQ15-8 (1 bits enable corresponding interrupt line)
EXTSMI7 Pin Status
EXTSMI6 Pin Status
EXTSMI5 Pin Status
EXTSMI4 Pin Status
EXTSMI3 Pin Status
EXTSMI2 Pin Status
EXTSMI Pin Status
TURBO Pin Status

-28-
Strap Options
Offset 95 - Power-Up Strap Option 1 ............................... RO
The following bits are latched from pins XD7-0 at power-up:
Offset 96 - Power-Up Strap Option 2 ............................... RO
These bits are latched from the indicated pins at power-up:
Note:
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Keyboard RP16 ............................ latched from XD7
Keyboard RP15 ........................... latched from XD6
Keyboard RP14 ........................... latched from XD5
Keyboard RP13 ........................... latched from XD4
PISA / SIO
Internal RTC Enable.................... latched from XD2
Internal PS2 Mouse Enable ......... latched from XD1
Internal KBC Enable ................... latched from XD0
User-Defined ............ latched from DACK7 (pin 133)
User-Defined ............ latched from DACK6 (pin 131)
User-Defined .............. latched from DACK5 (pin 58)
User-Defined .............. latched from DACK3 (pin 31)
User-Defined .............. latched from DACK2 (pin 33)
User-Defined .............. latched from DACK1 (pin 18)
EXTSMI2-7 SMI ...latched from ROMCS# (pin 135)
EXTSMI2-7 are on the same pins as DAC1-3,5-7
(pins 18, 33, 31, 58, 131, and 133) (see pin
definitions for more information)
IDE Addressing........... latched from SPKR (pin 134)
See also IDE offset 9 bits 0-3 for more information
External strap option values may be set by connecting
the indicated external pin to a 4.7K ohm pullup (for
1) or drive it low during reset with a 7407 TTL open
collector buffer (for 0) as shown in the suggested
circuit below:
0
1
0
1
0
1
0
1
0
1
0
1
Figure 2. Strap Option Circuit
PISA (for docking stations)
SIO (for desktop systems)........ (typical setting)
Disable
Enable
Disable
Enable
Disable
Enable
Enable external SMI on EXTSMI2-7
Disable external SMI on EXTSMI2-7
Fixed
Flexible
................................. latched from XD3
Register Descriptions
VT82C586A