vt82c586a ETC-unknow, vt82c586a Datasheet - Page 38

• Manufacturer Part Number: vt82c586a
• Description: Integrated Peripheral Controller
• Manufacturer: ETC-unknow

Offset 4B-48 - Drive Timing Control ............................... RW
The following fields define the Active Pulse Width and
Recovery Time for the IDE DIOR# and DIOW# signals:
The actual value for each field is the encoded value in the field
plus one and indicates the number of PCI clocks.
Offset 4C - Address Setup Time ....................................... RW
Offset 4E - Secondary Non-1F0 Port Access Timing ...... RW
Offset 4F - Primary Non-1F0 Port Access Timing` ........ RW
Preliminary Revision 0.1 October 13, 1996
31-28 Primary Drive 0 Active Pulse Width...... def=1010b
27-24 Primary Drive 0 Recovery Time............. def=1000b
23-20 Primary Drive 1 Active Pulse Width...... def=1010b
19-16 Primary Drive 1 Recovery Time............. def=1000b
15-12 Secondary Drive 0 Active Pulse Width .. def=1010b
11-8 Secondary Drive 0 Recovery Time ......... def=1000b
7-4
3-0
7-6
5-4
3-2
1-0
7-4
3-0
7-4
3-0
Secondary Drive 1 Active Pulse Width .. def=1010b
Secondary Drive 1 Recovery Time ......... def=1000b
Primary Drive 0 Address Setup Time
Primary Drive 1 Address Setup Time
Secondary Drive 0 Address Setup Time
Secondary Drive 1 Address Setup Time
For each field above:
DIOR#/DIOW# Active Pulse Width....... def=1111b
DIOR#/DIOW# Recovery Time.............. def=1111b
The actual value for each field is the encoded value in
the field plus one and indicates the number of PCI
clocks.
DIOR#/DIOW# Active Pulse Width....... def=1111b
DIOR#/DIOW# Recovery Time.............. def=1111b
The actual value for each field is the encoded value in
the field plus one and indicates the number of PCI
clocks.

00 1T
01 2T
10 3T
11 4T
.....................................................default
-32-
Offset 53-50 - UltraDMA33 Extended Timing Control . RW
Each byte defines UltraDMA33 operation for the indicated
drive. The bit definitions are the same within each byte.
Offset 61-60 - Primary Sector Size .................................. RW
Offset 69-68 - Secondary Sector Size .............................. RW
28-26 Reserved
25-24 Pri Drive 0 Cycle Time
20-18 Reserved
17-16 Pri Drive 1 Cycle Time
12-10 Reserved
15-12 Reserved
15-12 Reserved
11-0 Number of Bytes Per Sector ................ default=200h
11-0 Number of Bytes Per Sector ................ default=200h
9-8
4-2
1-0
31
30
29
23
22
21
15
14
13
7
6
5
Pri Drive 0 UltraDMA33-Mode Enable Method
Pri Drive 0 UltraDMA33-Mode Enable
Pri Drive 0 Transfer Mode ........................ read only
Pri Drive 1 UltraDMA33-Mode Enable Method
Pri Drive 1 UltraDMA33-Mode Enable
Pri Drive 1 Transfer Mode ........................ read only
Sec Drive 0 UltraDMA33-Mode Enable Method
Sec Drive 0 UltraDMA33-Mode Enable
Sec Drive 0 Transfer Mode........................ read only
Sec Drive 0 Cycle Time
Sec Drive 1 UltraDMA33-Mode Enable Method
Sec Drive 1 UltraDMA33-Mode Enable
Sec Drive 1 Transfer Mode........................ read only
Reserved
Sec Drive 1 Cycle Time
0
1
0
1
0
1
0
1
2
3
Enable by using “Set Feature” command..... def
Enable by setting bit-6 of this register
Disable................................................... default
Enable UltraDMA33-Mode Operation
Based on UltraDMA33 DMA mode ...... default
Based on UltraDMA33 PIO Mode
2T
3T
4T
5T
........................................ always reads 0
.................................................... default
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
Register Descriptions
VT82C586A