HEF4093BT,652 NXP Semiconductors, HEF4093BT,652 Datasheet - Page 6

• Manufacturer Part Number: HEF4093BT,652
• Description: IC SCHM TRIG NAND QD 2IN 14SOIC
• Manufacturer: NXP Semiconductors
• Series: 4000Br

Specifications of HEF4093BT,652

• Number Of Circuits: 4
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Logic Type: NAND Gate - Schmitt Trigger
• Number Of Inputs: 2
• Current - Output High, Low: 4.2mA, 4.2mA
• Voltage - Supply: 3 V ~ 15 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Product: NAND
• Logic Family: HEF4000
• High Level Output Current: - 4.2 mA
• Low Level Output Current: 4.2 mA
• Propagation Delay Time: 30 ns
• Supply Voltage (max): 15.5 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Logical Function: NAND
• Number Of Elements: 4
• Operating Supply Voltage (typ): 3.3/5/9/12V
• Operating Temp Range: -40C to 125C
• Package Type: SO
• Number Of Outputs: 1
• Technology: CMOS
• Mounting: Surface Mount
• Pin Count: 14
• Operating Temperature Classification: Automotive
• Quiescent Current: 1uA
• Operating Supply Voltage (max): 15V
• Operating Supply Voltage (min): 3V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 933373130652; HEF4093BTD; HEF4093BTD

NXP Semiconductors
12. Waveforms
Table 9.
Table 10.
HEF4093B
Product data sheet
Supply voltage
V
5 V to 15 V
Supply voltage
V
5 V to 15 V
Fig 4.
Fig 5.
DD
DD
Measurement points are given in
Logic levels: V
t
Propagation delay and output transition time
Test data given in
Definitions for test circuit:
DUT = Device Under Test.
C
R
Test circuit
r
, t
L
T
Measurement points
Test data
f
= load capacitance including jig and probe capacitance.
= termination resistance should be equal to the output impedance Z
= input rise and fall times.
OL
and V
Table
Input
V
V
OH
10.
I
SS
are typical output voltage levels that occur with the output load.
or V
output
DD
input
Table
Input
V
0.5V
All information provided in this document is subject to legal disclaimers.
G
M
V
V
0 V
OH
OL
9.
V
DD
I
V
10 %
Rev. 7 — 1 September 2010
I
90 %
R T
V
90 %
M
DUT
V
t
r
V
DD
10 %
M
t
PHL
t
t
≤ 20 ns
THL
r
, t
f
V
O
C L
o
of the pulse generator.
001aag182
t
f
001aag197
t
PLH
t
TLH
Quad 2-input NAND Schmitt trigger
V
0.5V
Output
M
DD
Load
C
50 pF
L
HEF4093B
© NXP B.V. 2010. All rights reserved.
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