74AHCT2G32DP,125 NXP Semiconductors, 74AHCT2G32DP,125 Datasheet

IC LOGIC GATE 2-INPUT-8PIN TSSOP

74AHCT2G32DP,125

Manufacturer Part Number
74AHCT2G32DP,125
Description
IC LOGIC GATE 2-INPUT-8PIN TSSOP
Manufacturer
NXP Semiconductors
Series
74AHCTr
Datasheet

Specifications of 74AHCT2G32DP,125

Logic Type
OR Gate
Number Of Inputs
2
Number Of Circuits
2
Current - Output High, Low
8mA, 8mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-TSSOP
Other names
504043-1P1 REV A
74AHCT2G32DP-G
74AHCT2G32DP-G
935274669125
Q2472696
1. General description
2. Features
3. Ordering information
Table 1.
Type number
74AHC2G32DP
74AHCT2G32DP
74AHC2G32DC
74AHCT2G32DC
74AHC2G32GD
74AHCT2G32GD
Ordering information
Package
Temperature range Name
40 C to +125 C
40 C to +125 C
40 C to +125 C
The 74AHC2G32; 74AHCT2G32 is a high-speed Si-gate CMOS device.
The 74AHC2G32; 74AHCT2G32 provides two 2-input OR gates.
I
I
I
I
I
I
I
74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
Rev. 02 — 20 January 2009
Symmetrical output impedance
High noise immunity
ESD protection:
Low power dissipation
Balanced propagation delays
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
N
N
N
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
TSSOP8
VSSOP8
XSON8U
Description
plastic thin shrink small outline package; 8 leads; body
width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3
2
0.5 mm
Product data sheet
Version
SOT505-2
SOT765-1
SOT996-2

Related parts for 74AHCT2G32DP,125

74AHCT2G32DP,125 Summary of contents

Page 1

Dual 2-input OR gate Rev. 02 — 20 January 2009 1. General description The 74AHC2G32; 74AHCT2G32 is a high-speed Si-gate CMOS device. The 74AHC2G32; 74AHCT2G32 provides two 2-input OR gates. 2. Features I Symmetrical output impedance I High ...

Page 2

... NXP Semiconductors 4. Marking Table 2. Marking Type number 74AHC2G32DP 74AHCT2G32DP 74AHC2G32DC 74AHCT2G32DC 74AHC2G32GD 74AHCT2G32GD 5. Functional diagram mna733 Fig 1. Logic symbol 6. Pinning information 6.1 Pinning 74AHC2G32 74AHCT2G32 GND 4 001aaj504 Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 74AHC_AHCT2G32_2 Product data sheet 74AHC2G32; 74AHCT2G32 ...

Page 3

... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin 1A 1B GND 4 1Y Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

Page 4

... NXP Semiconductors 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V) ...

Page 5

... NXP Semiconductors Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74AHCT2G32 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage 8 LOW-level output voltage 8 input leakage GND current 5 supply current 5 additional per input pin supply current ...

Page 6

... NXP Semiconductors Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure Symbol Parameter Conditions 74AHCT2G32 t propagation nA nY; see pd delay power per buffer; PD dissipation pF capacitance V = GND [ the same as t and PLH PHL [2] Typical values are measured at V [3] Typical values are measured at V ...

Page 7

... NXP Semiconductors negative positive Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 7. Test circuit for measuring switching times Table 10. Test data Type Input ...

Page 8

... NXP Semiconductors 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

Page 9

... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 10

... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 10. Package outline SOT996-2 (XSON8U) ...

Page 11

... Data sheet status Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74AHC2G32GD and 74AHCT2G32GD (XSON8U package). ...

Page 12

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 13

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 14 Abbreviations ...

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