vt83c469 ETC-unknow, vt83c469 Datasheet
vt83c469
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vt83c469 Summary of contents
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... VT83C469 PCMCIA Socket Controller DATA SHEET (Preliminary) DATE : March 13, 1995 VIA TECHNOLOGIES, INC. ...
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... PCMCIA interface. No external buffer is required between the ISA bus and PCMCIA bus. For systems requiring more than two sockets, the VT83C469 can be cascaded to support up to eight sockets without external logic. Under EEPROM IO resource data, the VT83C469 can support unlimited sockets under ISA Plug and Play ...
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... VT83C469 automatically disables VCC and VPP supplies to the socket. Interrupt Steering The VT83C469 steers the interrupt from the PC card to one of ten system interrupts. Multiple PC cards in a system can conflict if they try to utilize the same interrupt level. The VT83C469 can be programmed to eliminate this conflict by steering each PC card interrupt request to a different system interrupt ...
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... RESETDRV is true, this pin is used for input. The falling edge of RESETDRV latches the pull up or down state of this pin, and thereafter this pin is used for normal operation. The VT83C469 will not respond to a data register read or write operation index register read operation unless the index register has first been written to with a valid index ...
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... The access is not a DMA transfer. AEN = 0 to access the I/O PC Card. Mixed Voltage Operation The VT83C469 has three power planes: the ISA bus interface, socket A interface and socket B interface. The ISA bus power planes connect to the core power plane and supports 5v operation. Socket A and socket B power planes each can be independently connected ...
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... I/O BASE ADDRESS 0 [7:0] PC Card DMA Operations The VT83C469 supports the use card as an interface with a DMA device. The VT83C469 defines an extension to the I/O card definition that allows ISA compatible DMA operation, including the Terminal Count signal required by the standard ISA floppy disk controller. ...
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... The PCMCIA interface signals are redefined as the DMA interface signals according to the following table 61,132 54,125 49,120 1,72 16,87 30,100 DMA ODE OCKET IDE IGNAL EFAULT IN LTERNATE F UNCTION IOIS16# SPKR# INPACK# REG# OE# WE# 7 Preliminary VT83C469 UNCTION DREQ# DREQ# DREQ# DACK TC# TC# ...
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... VIA Technologies, Inc. Register Set The following is a list of VT83C469 registers and their offset values. The General Registers, Interrupt Registers, I/O Registers and Memory Registers are fully compatible with the Intel 82365SL. The other registers are unique to the VT83C469 OCKET ...
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... HIP ONTROL EGISTERS Identification and Revision Register ( Read Only ) Address : Index ( Base + 00h ) B IT D[7:6] VT83C469 Interface Type Type of PC Card supported by the socket. These bits do not identify the type of card that is present at the socket. 00: I/O only. 01: Memory only. 10: Memory & I/O. 11: Reserved. D[5:4] Reserved. These bits will be read back as zero. ...
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... For I/O PC Cards, bit 0 indicates the current status of the (STSCHG/RI#) signal from the PC Card when the ring indicate enable bit in the Interrupt and General control register is set to 0. Preliminary VT83C469 F UNCTION 10 ...
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... F UNCTION A UTO P CD1# CD2 OWER RI STATE S O WITCH UTPUTS E NABLE OFF OFF OFF OFF OFF OFF OFF 11 Preliminary VT83C469 PC C ARD P OWER A CTIVE ...
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... F UNCTION IRQ BIT NTERRUPT EQUEST 0 IRQ not select 1 Reserved 0 Reserved 1 IRQ3 enable 0 IRQ4 enable 1 IRQ5 enable 0 Reserved 1 IRQ7 enable 0 Reserved 1 IRQ9 enable 0 IRQ10 enable 1 IRQ11 enable 0 IRQ12 enable 1 Reserved 0 IRQ14 enable 1 IRQ15 enable 12 Preliminary VT83C469 L EVEL ...
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... Reading the Card Status Change Register causes the register bits to be reset to zero. If the card status change interrupt is enabled to one of the system bus interrupt request lines, the corresponding IRQ signal remains active high until this register is read. Preliminary VT83C469 F UNCTION 13 ...
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... For memory PC Cards, enables a card status change interrupt when a battery dead condition has been detected. For I/O PC Cards, enables the VT83C469 to generate a card status change interrupt if the STSCHG# signal has been pulled low by the I/O PC Card, assuming that the Ring Indicate Enable bit is set zero. ...
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... When the system address is within the window, the computed address will be generated to the PC Card. NOTE: The start, stop and offset registers pairs must all be set to the desired window values before setting bit to one.( All Memory Windows ). Preliminary VT83C469 F UNCTION 15 ...
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... This provides a minimum 1 byte window for I/O address window. I/O Address Start Register High Byte ( Read/Write ) Address : Window 0 Index ( Base + 09h ) Address : Window 1 Index ( Base + 0Dh ) B IT D[7:0] I/O Window Start Address A[15:8] High order address bits used to determine the start address of the corresponding I/O address window. Preliminary VT83C469 F UNCTION F UNCTION F UNCTION 16 ...
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... System memory access will occur with no additional wait states and the NOWS# signal will be returned to the system bus. The WAIT# signal from PC Card will override this bit. D[5:4] R/W. 00 D[3:0] System Memory Window Start Address A23:20. High order address bits used to determine the start address of the corresponding system memory address mapping window. Preliminary VT83C469 F UNCTION F UNCTION F UNCTION F ...
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... Address : Window 1 Index ( Base + 1Ch ) Address : Window 2 Index ( Base + 24h ) Address : Window 3 Index ( Base + 2Ch ) Address : Window 4 Index ( Base + 34h ) B IT D[7:0] System Memory Window Offset Address A[19:12] Low order address bits which added to the system address bits A19:12 to generate card address. Preliminary VT83C469 F UNCTION F UNCTION F UNCTION 18 ...
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... When this bit is "1," the 3. determined by the DET_5 pin This bit is connected to PCMCIA pin 43. Cards that will operate at 3.3v will drive this pin to a "0." Preliminary VT83C469 F UNCTION F UNCTION CC is applied to the PC card. When this bit is "0," 3.3v or ...
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... B IT D[7:6] Chip Identification. ( Read Only ) This field identifies the VT83C469 device and compatible with Cirrus Logic CL-6722 device. For the first read of this register this field will be 11h; on the next read will be 00h. D5 Dual/Single Socket. ( Read Only ) This bit will be 1b, because the VT83C469 is support two sockets. ...
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... The PC Card SPKR# pin will be used to drive IRQ12 if Drive LED Enable is set. D0 ATA Mode. 0: Normal operation. 1: Configures the socket interface to handle ATA type III disk drives. VIA ID Register (Read) Address: Index (Base + 2Eh [7:4] Major Version R. 1000 D [3:0] Minor Version R. 0001 Preliminary VT83C469 F UNCTION F UNCTION 21 ...
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... WP/IOIS16# 11: BVD2/SPKR# D5 Reserved. D4 DMA Data Size 0: During DMA read/write cycles, data size is 8-bit. 1: During DAM read/write cycles, data size is 16-bit. The I/O window data size bit in I/O control register and the IOIS16# signal are irrelevant during actual DMA cycles. D [3:0] Reserved. Preliminary VT83C469 F UNCTION 22 ...
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... CE#1, CE#2 allows 8-bit hosts to access all data on Card Data [7:0] if desired. I CLK System Clock VT83C469 ESCRIPTION D ESCRIPTION High during DMA cycles, low These signals indicate the health of the The signals are connected to 23 Preliminary VT83C469 YPE 204 I 205 I 54, 125 I 52, 123 I 15,19, 21, 23- O ...
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... A 16-bit to 8-bit conversion is done inactive. I MEMR# Active low signal indicated a memory read cycle. MEMW# I Active low signal indicates a memory write cycle. S OE# Active low signal used to gate memory reads from memory cards. Preliminary VT83C469 D ESCRIPTION Active low output requesting YPE 2, 4-10, 12, 13, ...
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... System Data Bus. I SIOR# This active low I/O read signal instructs the VG-468 to drive data onto the data bus. I SIOW# This active low I/O write signal instructs the VG-468 to latch the data on the data bus. Preliminary VT83C469 D ESCRIPTION RIO# will be functional in CS YPE ...
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... Zero Wait State. An active low output indicates that the PC Card wishes to terminate the present bus cycle without inserting additional wait states. This cycle will not be driven during a 16- bit I/O access. S A_Vcc Socket A power signal for 3. B_Vcc Socket B power signal for 3. Preliminary VT83C469 D ESCRIPTION YPE 153 I/O ...
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... MEMCS16# B_CA14 150 IOCHRY B_CA19 151 RIO# B_WE# 152 INTR# B_3VEN 153 SPKROUT# B_CA20 154 GND B_RDY 155 SD15 B_CA21 156 SD14 27 Preliminary VT83C469 AME 157 SD13 158 SD12 159 SD11 160 SD10 161 SD9 162 SD8 163 ...
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... VIA Technologies, Inc. VT83C469 P Preliminary VT83C469 D IN IAGRAM 28 ...
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... IL I Tristate leakage current OZ I Power supply current CC C LECTRICAL HARACTERISTICS Absolute Maximum Ratings Min Max 0 70 -55 125 -0.5 5.5 -0.5 5.5 DC Characteristics Min Max -.50 0.8 2 0.45 2 +/-10 - +/- Preliminary VT83C469 Unit Unit Condition =4.0mA =-1.0mA OH uA 0<V < 0.45<V <V OUT DD mA ...
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... ISA Read CMD Falling to Data Output T19 CE#, REG# Setup to Socket CMD Setup T20 ISA CMD Inactive to Socket CMD Inactive Valid Delay T21 Socket CMD Inactive to CADR <25:12> Hold Time T22 CA <15:12> Hold from A <15:12> Memory T22 CA<15:12> Hold from A<15:12> I/O Preliminary VT83C469 Description 30 Min Max 102 162 ...
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... EXT_DIR Hold from ISA Read Inactive T26 AEN Valid to ISA CMD Active Setup T27 AEN Hold from ISA Command Inactive T28 RI_to RI_OUT Delay T29 SPKR_ to SPKR_OUT Delay T30 Card Status Change to IRQ# Valid T31 PCMCIA IREQ# to IRQx Delay Preliminary VT83C469 BUSCLK 24 ...
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... VIA Technologies, Inc. Memory: Standard/Extended SYSCLK LA<23:17> SA<16:0>,SHBE# MEMR#,MEMW# MEMCS16# IOCHRDY CADR<25:12> CE#,REG# OE#,WE# WAIT# Ext_DIR Preliminary VT83C469 T1 Valid Address Valid Address T11 T10 T30 Valid Address T19 T13 T23 T24 T17 T18 32 T7 T22 T20 T21 T14 T25 ...
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... VIA Technologies, Inc. IO: Standard / Extended BUSCLK LA<23:17> SA<16:0>,SHBE# IOR#,IOW# IOCS16# IOCHRDY CADR<25:12> CE#,REG# IORD#,IOWR# IOIS16# WAIT# Ext_DIR Preliminary VT83C469 Valid Address Valid Address T5 T8 T11 T10 T12 Valid Address T19 T31 T15 T17 T18 T23 T24 T16 T22 T20 ...
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... VIA Technologies, Inc. Interrupt, Ring Indicate, Speaker Timings STSCHG(RI)# Card Status Change IREQ# IRQx RI_OUT# SPKR# SPKR_OUT# AEN Setup and Hold AEN# ISA:I/O CMD Preliminary VT83C469 T28 T30 T31 T29 T29 T27 T26 34 T28 ...
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... VIA Technologies, Inc. 208-Pin Plastic Flat Package 156 0.85TYP 157 208 1 0.85TYP 0.5 0.1 +0.1 0.15 -0.05 Preliminary VT83C469 30.6+/-0.2 27.2+/-0.4 0.2+/-0.1 0.08 M 29.6+/-0.4 o 0~10 0.5+/-0.2 35 105 104 27.2+/-0.4 30.6+/-0 3.35+/-0.4 4.60MAX +0.3 0.55 -0.2 ...
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... VIA Technologies, Inc VT83C469 DITOR P S RODUCT PECIFICATIONS P D ROJECT ESIGNER F A INAL PPROVAL ROJECT IGN FF HEET R RELIMINARY N S AME Alex Tsao Jeffery Chang Huang Yu-Chung Tzu-Mu Lin 36 Preliminary VT83C469 ELEASE D IGNATURE ATE ...