m12l16161a Elite Semiconductor Memory Technology Inc., m12l16161a Datasheet
m12l16161a
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m12l16161a Summary of contents
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... DD Elite Semiconductor Memory Technology Inc. GENERAL DESCRIPTION The M12L16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized 524,288 words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle ...
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... CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS , WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. M12L16161A LWE LDQM DQi LDQM LWCBR L(U)DQM Input Function Publication Date : Sep ...
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... ≤ 10ns acceptable. ≤ 10ns acceptable 0.3V, all other pins are not under test = 0V. DD ≤ V VDD. OUT = 1MHz) ° Symbol C CLK ADD C OUT M12L16161A Value -1.0 ~ 4.6 -1.0 ~ 4.6 - 150 0.7 50 ° Typ Max Unit 3.3 3.6 V 3 0.4 ...
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... CLK V (max Input signals are stable I = 0Ma, Page Burst OL All Band Activated (min) CCD CCD ≥ (min ≤ CKE 0.2V M12L16161A C V (min)/V (max)=2.0V/0.8V CAS Version Latency -5 -7 130 100 2 ∞ =15ns 25 ∞ ∞ ...
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... RP t (min) 30 RAS t (max) RAS t (min (min) CDL t (min) RDL t (min) BDL t (min) CCD CAS latency=3 CAS latency=2 M12L16161A Value 2.4 / 0.4 1 1.4 See Fig.2 Output Z0=50 Ω (Fig.2) AC Output Load Circuit Version - 100 Publication Date : Sep. 2008 Revision : 2 ...
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... SAC - 2 2 SLZ - 5 SHZ - 5.5 - *All AC parameters are measured from half to half. M12L16161A -7 Unit Note Max 1000 Publication Date : Sep. 2008 Revision : 2.7 6/29 ...
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... RAS WE M12L16161A JEDEC Standard Test Set (refresh counter test) Burst Read and Single Write (for Write Through Cache) Use in future Vender Specific Mode Register Set Bit2-0 000 001 010 Burst length 011 100 101 110 ...
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... M12L16161A Interleave Addressing Sequence (decimal Interleave Addressing Sequence (decimal ...
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... L L Exit Entry Exit (V= Valid, X= Don’t Care, H= Logic High , L = Logic Low) after the end of burst. RP M12L16161A DQM BA A10/AP A9~A0 Note RAS CAS ...
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... *Note M12L16161A *Note2,3 *Note4 *Note2 *Note 3 *Note4 ...
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... Enable auto precharge, precharge bank A at end of burst. 1 Enable auto precharge, precharge bank B at end of burst. 4.A10/AP and BA control bank precharge when precharge command is asserted. A10/AP BA precharge 0 0 Bank Bank Both Banks Elite Semiconductor Memory Technology Inc. Operation M12L16161A Publication Date : Sep. 2008 Revision : 2.7 11/29 ...
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... Elite Semiconductor Memory Technology Inc M12L16161A Publication Date : Sep ...
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... Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Qa3 Precharge (A- Bank) ) after the clock. SHZ +CAS latency-1)+t RCD M12L16161A Cb0 Rb Db1 Db2 Db0 *Note4 Db0 Db2 Db1 *Note4 Row Active W r ite ...
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... HIGH Cb0 Qa0 Qb0 Qb1 Qb2 Qa1 Qa1 Qb0 Qb1 Qa0 *Note1 Read (A-Bank) before Row precharge, will be written. RDL M12L16161A *Note2 Cc0 Cd0 t RDL Dc0 Dc1 Dd1 Dd0 Dc0 Dc1 Dd0 Dd2 t CDL *Note3 ...
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... HIGH RBb CBb RBb QAa0 QAa1 QAa2 QAa3 QBb0 QAa0 QAa1 QAa3 QAa2 Read (B-Bank) Row Active (B-Bank) M12L16161A CAc CBd CAe QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QBb1 QBb0 QBb2 QBb3 QAc0 QAc1 QBd0 ...
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... Elite Semiconductor Memory Technology Inc HIGH CBb RBb RBb DBb2 DBb3 DAa1 DAa2 DAa3 DBb0 DBb1 t CDL Write (B-Bank) (B-Bank) M12L16161A *Note2 CAc CBd DAc0 DAc1 DBd0 DBd1 t RDL *Note1 Precharge Write (Both Banks) (A-Bank) Write (B-Bank) Publication Date : Sep ...
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... ESMT Read & Write Cycle at Different Bank @ Burst Length = 4 *Note: 1.t should be met to complete write. CDL Elite Semiconductor Memory Technology Inc. M12L16161A Publication Date : Sep. 2008 Revision : 2.7 17/29 ...
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... Read with Auto Precharge Auto Precharge Start Point ( A - Bank ) ( A - Bank) before internal precharge start RAS M12L16161A ...
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... Elite Semiconductor Memory Technology Inc M12L16161A ...
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... *Note2 M12L16161A ...
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... Elite Semiconductor Memory Technology Inc M12L16161A Publication Date : Sep ...
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... Row Active (B-Bank) Read with Auto Precharge (A-Bank) M12L16161A * ...
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... Row Active Precharge Active Power-Down Power-down Exit Entry M12L16161A Read Active Power-down Exit Publication Date : Sep. 2008 Revision : 2 ...
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... Elite Semiconductor Memory Technology Inc *Note3 RAS M12L16161A ...
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... CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register. 2.Minimum 2 clock cycles should be met before new RAS activation. 3.Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. Auto Refresh Cycle M12L16161A ...
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... SEATING PLANE Nom Max - 1.20 0.127 0.203 1.00 1.05 - 0.45 0.35 0.40 - 0.21 0.127 0.16 20.95 21.08 11.76 11.96 10.16 10.29 0.50 0.60 0.80 REF 0.80 BSC - 0 M12L16161A B B1 WITH PLATING BASE METAL SECTION Y-Y GAGE PLANE θ° DETAIL "A" Dimension in inch Min Nom - - 0.002 0.005 0.037 0.039 0.012 - 0.012 0.014 0.005 - 0.004 0.005 0.820 0.825 0.455 ...
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... Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Dimension in mm Min Norm Max Min 1.00 0.20 0.25 0.30 0.008 0.61 0.66 0.71 0.024 0.30 0.35 0.40 0.012 6.30 6.40 6.50 0.248 10.00 10.10 10.20 0.394 3.90 9.10 0.65 M12L16161A Dimension in inch Norm Max 0.039 0.010 0.012 0.026 0.028 0.014 0.016 0.252 0.256 0.398 0.402 0.154 0.358 0.026 Publication Date : Sep. 2008 Revision : 2.7 27/29 ...
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... Delete –5.5, -6, -8, -10 AC spec Add 60V FBGA Modify VFBGA 60Ball Total high spec Delete BGA ball name of packing dimensions Modify Pin Configuration (TOP VIEW) Modify tRAS(min) 40ns => 30ns and tRC(min) 55ns => 48ns Add Y spec. into TSOPII package dimension M12L16161A Description 2ea , spec CC3N ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice M12L16161A Publication Date : Sep. 2008 Revision : 2.7 29/29 ...