UPD75238GJ

Manufacturer Part NumberUPD75238GJ
Description4 BIT SINGLE-CHIP MICROCOMPUTER
ManufacturerNEC [NEC]
UPD75238GJ datasheet
 
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Page 107/190

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(7) Manipulation of SCK0 pin output
The SCK0/P01 pin has a built-in output latch, so that this pin allows static output by software manipulation
in addition to normal serial clock output.
The number of SCK0s can be software-set arbitrarily by manipulating the P01 output latch. (The SO0/
SB0/SB1 pin is controlled by manipulating the RELT and CMDT bits of SBIC.)
The procedure for manipulating SCK0/P01 pin output is explained below.
Set serial operation mode register 0 (CSIM0) (SCK0 pin: output mode, serial operation: enabled).
1
When serial transfer operation is halted, SCK0 from the serial clock control circuit is set to 1.
Manipulate the P01 output latch by using a bit manipulation instruction.
2
Example
To output one clock cycle on the SCK0/P01 pin by software
SEL
MB15
MOV
XA, #10000011B ; SCK0 (f
MOV
CSIM0, XA
CLR1
0FF0H.1
SET1
0FF0H.1
Fig. 4-58 SCK0/P01 Pin Circuit Configuration
P01/SCK0
When CSIE0=1 and CSIM01
and CSIM00 are not 00
The P01 output latch is mapped to bit 1 of address FF0H. A RESET signal sets the P01 output latch to 1.
Cautions 1.
During normal serial transfer operation, the P01 output latch must be set to 1.
2.
The P01 output latch cannot be addressed by specifying PORT0.1 (as described below). The
address of the latch (0FF0H.1) must be coded in the operand of an instruction directly.
However, MBE = 0 (or MBE = 1, MBS = 15) must be specified before the instruction is
executed.
CLR1 PORT0.1
SET1 PORT0.1
CLR1 0FF0H.1
SET1 0FF0H.1
; or CLR1 MBE
3
/2
), output mode
X
; SCK0/P01
0
; SCK0/P01
1
Address
FF0H.1
P01
To internal circuit
output
latch
SCK0
Not allowed
Allowed
PD75238
From the serial clock
control circuit
107