UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 133

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UPD75238GJ

Manufacturer Part Number
UPD75238GJ
Description
4 BIT SINGLE-CHIP MICROCOMPUTER
Manufacturer
NEC [NEC]
Datasheet
5.2 HARDWARE OF THE INTERRUPT CONTROL CIRCUIT
(1) Interrupt request flag and interrupt enable flag
There are ten interrupt request flags (IRQ
or test source; there are 8 interrupt and 2 test sources.
INT0 interrupt request flag (IRQ0)
INT1 interrupt request flag (IRQ1)
INT2 interrupt request flag (IRQ2)
INT4 interrupt request flag (IRQ4)
BT interrupt request flag (IRQBT)
The interrupt request flag is set to 1 when an interrupt request is issued, and is automatically cleared to
0 when the CPU is interrupted. Since the IRQBT and IRQ4 share the vector address, the clear operation
varies. (See Section 5.5.)
There are ten interrupt enable flags (IE
request flag.
INT0 interrupt enable flag (IE0)
INT1 interrupt enable flag (IE1)
INT2 interrupt enable flag (IE2)
INT4 interrupt enable flag (IE4)
BT interrupt enable flag (IEBT)
When an interrupt request flag is set, the interrupt enable flag corresponding to that interrupt request flag
enables the request interrupt. When an interrupt request flag is cleared, the interrupt enable flag
corresponding to that interrupt request flag disables the interrupt.
When an interrupt request flag is set and its corresponding interrupt enable flag enables the requested
interrupt, a vector interrupt request (VRQn) is issued. This signal is also used for releasing the standby
mode.
The interrupt request flags and interrupt enable flags are manipulated with bit manipulating instructions
and 4-bit memory manipulation instructions. When a bit manipulation instruction is used, the flags can
always be manipulated directly irrespective of the MBE setting. The interrupt enable flags are manipulated
with EI IE
and DI IE
instructions. An SKTCLR instruction is normally used to test an interrupt request
flag.
When an interrupt request flag is set with an instruction, a vector interrupt is executed irrespective of
whether an interrupt occurs.
A RESET input clears an interrupt request flag and its corresponding interrupt enable flag to 0 and all
interrupts are disabled.
), listed below, each corresponding to a particular interrupt
Serial interface interrupt request flag (IRQCSI0)
Timer/event counter interrupt request flag (IRQT0)
Timer/pulse generator interrupt request flag (IRQTPG)
Key scan interrupt request flag (IRQKS)
Clock timer interrupt request flag (IRQW)
), listed below, each corresponding to a particular interrupt
Serial interface interrupt enable flag (IECSI0)
Timer/event counter interrupt enable flag (IET0)
Timer/pulse generator interrupt enable flag (IETPG)
Key scan interrupt enable flag (IEKS)
Clock timer interrupt enable flag (IEW)
PD75238
133

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