UPD75238GJ

Manufacturer Part NumberUPD75238GJ
Description4 BIT SINGLE-CHIP MICROCOMPUTER
ManufacturerNEC [NEC]
UPD75238GJ datasheet
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
Page 131
132
Page 132
133
Page 133
134
Page 134
135
Page 135
136
Page 136
137
Page 137
138
Page 138
139
Page 139
140
Page 140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
Page 134/190

Download datasheet (2Mb)Embed
PrevNext
Table 5-2 Set Signals of Interrupt Request Flags
Interrupt
request flag
IRQBT
Set by a reference time interval signal from the basic interval timer.
IRQ4
Set by a detected rising or falling edge of an INT4/P00 pin input signal.
IRQ0
Set by a detected edge of an INT0/P10 pin input signal. The detection edge is specified
by the INT0 mode register (IM0).
IRQ1
Set by a detected edge of an INT1/P11 pin input signal.
by the INT1 mode register (IM1).
IRQCSI0
Set by a serial data transfer completion signal for the serial interface.
IRQT0
Set by a match signal from timer/event counter 0.
IRQTPG
Set by a match signal from the timer/pulse generator.
IRQKS
Set by a key scan timing signal from the display controller.
IRQW
Set by a signal from the clock timer.
IRQ2
Set by a detected rising edge of an INT2/P12 pin input signal.
(2) Noise eliminator and edge detection mode register
As shown in Fig. 5-2 and Fig. 5-3, the INT0, INT1, and INT2 pins are configured as external interrupt input
pins that enable detection edge selection.
In addition, INT0 is provided with a noise elimination function based on a sampling clock. Basically, the
noise eliminator eliminates pulses narrower than two sampling clock cycles
accept pulses wider than one sampling clock cycle as interrupt signals depending on the sampling timing.
It surely accepts pulses wider than two sampling clock cycles as interrupt signals.
INT0 has two sampling clocks
and f
edge detection mode register (see Fig. 5-4).
The IRQ2 is set by detecting a rising edge of the INT2 pin input.
The edge detection mode registers (IM0 and IM1) used to select a detection edge have the format shown
in Fig. 5-4. A 4-bit memory manipulation instruction is used to set IM0 or IM1. A RESET input clears all
bits to 0, and a rising edge is selected for INT0, INT1, and INT2.
Note When a sampling clock is
When a sampling clock is f
Cautions 1. Since the INT0 pin input is sampled with a clock, INT0 does not operate in a standby mode.
2. When INT0/P10 is used as a port, pulses input from INT0/P10 go through the noise
eliminator. So the input pulses must be wider than two sampling clock cycles.
134
Set signal of interrupt request flag
The detection edge is specified
/64, either of which can be selected according to bit 3 (IM03) of the
X
, two sampling clock cycles are 2t
.
CY
/64, two sampling clock cycles are 128/f
X
PD75238
Interrupt
enable flag
IEBT
IE4
IE0
IE1
IECSI0
IET0
IETPG
IEKS
IEW
IE2
Note
as noise. However, it may
.
X