UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 143
UPD75238GJ
Manufacturer Part Number
UPD75238GJ
Description
4 BIT SINGLE-CHIP MICROCOMPUTER
Manufacturer
NEC [NEC]
Datasheet
1.UPD75238GJ.pdf
(190 pages)
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(A STOP instruction sets bit 3 of PCC, and a HALT instruction sets bit 2 of PCC.)
the time when PCC is rewritten to the time when the CPU clock signal is changed as indicated in Table 4-1.
When changing an operation clock pulse before the standby mode or a CPU clock signal after the standby mode
is released, it is necessary to rewrite PCC and set the standby mode after the number of machine cycles
required to change the CPU clock pulse elapses.
including general registers, flags, mode registers, and output latches, are retained.
A STOP instruction is used to set the STOP mode, and a HALT instruction is used to set the HALT mode.
When changing a CPU operation clock pulse with the low-order two bits of PCC, a time lag may occur from
In a standby mode, the contents of all registers and data memory that are stopped during the standby mode,
Cautions 1. When the STOP mode is set, the X1 input is internally connected to V
2. An interrupt request signal is used to release a standby mode.
suppress leakage at the crystal oscillator circuitry. This means that the STOP mode cannot
be used with a system that uses an external clock.
This means that if an interrupt source whose interrupt request flag and interrupt enable flag
are both set exists, the initiated standby mode is released immediately after it is set. When
the STOP mode is set, therefore, the PD75238 enters the HALT mode immediately after the
STOP instruction is executed, then returns to the operation mode after the wait time specified
by the BTM register has elapsed.
SS
(GND potential) to
PD75238
143
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