UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 145
UPD75238GJ
Manufacturer Part Number
UPD75238GJ
Description
4 BIT SINGLE-CHIP MICROCOMPUTER
Manufacturer
NEC [NEC]
Datasheet
1.UPD75238GJ.pdf
(190 pages)
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(d) Release of the HALT mode by the occurrence of an interrupt
before clock generation is started following the release of the STOP mode, regardless of whether the STOP
mode is released by RESET signal input or the generation of an interrupt.
Table 6-2.)
The wait times used when the STOP mode is released do not include a time (a in the figure below) required
When the STOP mode is released by the occurrence of an interrupt, a wait time is determined by BTM. (See
Note This time does not include the time from the release of the STOP mode to the start of oscillation.
Remark The dashed line indicates the case where the interrupt request that releases the standby
Standby
release
signal
Clock
(When f
(When f
mode is accepted (IME = 1).
Other than above
Other than above
BTM3
BTM3
–
–
–
–
–
–
–
–
Operating mode
X
X
= 6.0 MHz)
= 4.19 MHz)
BTM2
BTM2
0
0
1
1
0
0
1
1
HALT instruction
Wave-form
at the X1 pin
Table 6-2 Selection of a Wait Time with BTM
BTM1
BTM1
0
1
0
1
0
1
0
1
V
SS
BTM0
BTM0
HALT mode
0
1
1
1
0
1
1
1
Wait time
STOP mode release
Wait time
Approx. 2
Use prohibited
Approx. 2
Approx. 2
Approx. 2
Approx. 2
Approx. 2
Approx. 2
Approx. 2
Use prohibited
Oscillation
Note
Note
a
20
17
15
13
20
17
15
13
/f
/f
/f
/f
/f
. ( ) indicates the value for f
/f
/f
/f
. ( ) indicates the value for f
X
X
X
X
X
X
X
X
(Approx. 250 ms)
(Approx. 31.3 ms)
(Approx. 7.82 ms)
(Approx. 1.95 ms)
(Approx. 175 ms)
(Approx. 21.8 ms)
(Approx. 5.46 ms)
(Approx. 1.37 ms)
Operating mode
X
X
= 4.19 MHz
= 6.0 MHz
PD75238
145
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