UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 38

• Manufacturer Part Number: UPD75238GJ
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC [NEC]

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(4) Memory bank enable flag (MBE)
(5) Register bank enable flag (RBE)
The memory bank enable flag is a 1-bit flag used to specify the address information generation mode for
the high-order four bits of a 12-bit data memory address.
When the MBE is set to 1, the data memory address space is expanded, allowing all data memory space
to be addressed.
When the MBE is reset to 0, the data memory address space is fixed, regardless of MBS setting. (See Fig.
2-1.)
A RESET input automatically initializes the MBE by setting the MBE to the content of bit 7 at program
memory address 0.
In vectored interrupt processing, the MBE is automatically set to the content of bit 7 in the vector address
table for servicing the interrupt.
Usually, the MBE is set to 0 in interrupt processing, and static RAM in memory bank 0 is used.
The register bank enable flag is a 1-bit flag used to determine whether to expand the general register bank
configuration.
When the RBE is set to 1, a set of general registers can be selected from register banks 0 to 3, depending
on the setting of the register bank select register (RBS).
When the RBE is reset to 0, register bank 0 is always selected as general registers, regardless of the setting
of the RBS.
A RESET input automatically initializes the RBE by setting the RBE to the content of bit 6 at program
memory address 0.
When a vectored interrupt occurs, the RBE is automatically set to the content of bit 6 in the vector address
table for servicing the interrupt. Usually, the RBE is set to 0 in interrupt processing. Register bank 0 is
used for 4-bit processing, and register banks 0 and 1 are used for 8-bit processing.
PD75238