UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 67

• Manufacturer Part Number: UPD75238GJ
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC [NEC]

(3) Operation mode of the timer/event counter
The timer/event counter operates in the count operation disable mode or in the count operation mode,
depending on the setting of the mode register.
The following operations are possible, regardless of the setting of the mode register:
(iii) Setting of the modulo register (TMOD0)
(iv) Reading from the count register (T0)
(b) Count operation mode
(a) Count operation disable mode
(ii) Output of the timer out F/F status to the PTO0
(v) Setting, clearing, and testing of the interrupt request flag (IRQT0)
(i) P13/TI0 pin signal input and test
TI0
This mode is set when bit 2 of TM0 is set to 0. In this mode, count operation is not performed because
count pulse (CP) supply to the count register is stopped.
This mode is set when bit 2 of TM0 is set to 1. In this mode, a count pulse signal selected with bits
4 to 6 is supplied to the count register for count operation as shown in Fig. 4-28.
Timer operation is usually started in the following steps:
1
2
An 8-bit data transfer instruction is used to set the modulo register.
Internal
clock
A count value is set in the modulo register (TMOD0).
An operation mode, count clock, and start instruction are set in the mode register (TM0).
Fig. 4-28 Operation in the Count Operation Mode
MPX
CP
Modulo register
Count register
Comparator
(TMOD0)
(T0)
INTT0
(IRQT0 set signal)
Clear
Match
TOUT
F/F
To serial interface (channel 0)
PD75238
PTO0
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