UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 96
Manufacturer Part Number
4 BIT SINGLE-CHIP MICROCOMPUTER
(5) Serial interface (channel 0) operation
(a) Operation halt mode
The operation halt mode is used when serial transfer is not performed. This mode reduces power
The shift register 0 does not perform shift operation in this mode, so the shift register can be used
as a normal 8-bit register.
A RESET input sets the operation halt mode. The P02/SO0/SB0 pin and P03/SI0/SB1 pin function as
input-only port pins. The P01/SCK0 pin can be used as an input port pin by setting the serial operation
mode register 0.
(b) Three-wire serial I/O mode operations
The three-wire serial I/O mode is compatible with other modes used in the 75X series and 78K series.
Communication is performed using three lines: Serial clock (SCK0), serial output (SO0), and serial
The three-wire serial I/O mode transfers data, with eight bits as one block. Data is transferred
bit by bit in phase with the serial clock.
The shift register performs shift operation on the falling edge of the serial clock (SCK0). Send
data is latched on the SO0 latch, and is output on the SO0 pin. Receive data applied to the SI0
pin is latched in the shift register 0 on the rising edge of SCK0.
When eight bits have been transferred, shift register 0 operation automatically terminates setting
the interrupt request flag (IRQCSI0).
Fig. 4-49 Timing of Three-Wire Serial I/O Mode
Transfer operation is started in phase with falling edge of SCK0.
Execution of instruction that writes data to SIO0 (Transfer operation start specification)
Completion of transfer