S-75V14ANC-5VA-TFG Seiko Instruments, S-75V14ANC-5VA-TFG Datasheet
S-75V14ANC-5VA-TFG
Specifications of S-75V14ANC-5VA-TFG
Available stocks
Related parts for S-75V14ANC-5VA-TFG
S-75V14ANC-5VA-TFG Summary of contents
Page 1
... CMOS low power consumption to achieve ultra high speed operation correspond to LSTTL IC’s. All gates of the internal circuitry have buffered outputs to ensure high noise immunity and output stability. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and V . ...
Page 2
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 2 Environmental code ...
Page 3
... V IH Input voltage “L” level “H” level Output voltage “L” level Input current Current consumption MINI LOGIC SERIES 2 INPUT NAND GATE Symbol OUT 0 to 100 ( Conditions V CC 2.0 ⎯ 5 2.0 ⎯ 5.5 2.0 = −50 μ ...
Page 4
... Symbol t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 5
... CMOS low power consumption to achieve ultra high speed operation correspond to LSTTL IC’s. All gates of the internal circuitry have buffered outputs to ensure high noise immunity and output stability. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and V . ...
Page 6
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 6 Environmental code ...
Page 7
... V IH Input voltage “L” level V IL “H” level Output voltage V IN “L” level Input current Current consumption MINI LOGIC SERIES 2 INPUT NOR GATE Symbol OUT 0 to 100 ( Conditions V CC 2.0 ⎯ 5 2.0 ⎯ 5.5 2.0 = −50 μ ...
Page 8
... Symbol t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 9
... CMOS low power consumption to achieve ultra high speed operation correspond to LSTTL IC’s. The special purpose unbuffered circuit design is suitable for a wide variety of linear circuits. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and V ...
Page 10
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 10 Environmental code ...
Page 11
... Rev.3.0 _00 Recommended Operating Conditions Item Power voltage Input voltage Output voltage Input rise / fall time DC Electrical Characteristics Item Symbol “H” level V IH Input voltage “L” level V IL “H” level Output voltage “L” level Input current Current consumption I ...
Page 12
... Symbol t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 13
... CMOS low power consumption to achieve ultra high speed operation correspond to LSTTL IC’s. The special purpose unbuffered circuit design is suitable for a wide variety of linear circuits. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and V ...
Page 14
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 14 Environmental code ...
Page 15
... OUT Input voltage “L” level OUT V IN “H” level Output voltage V IN “L” level Input current Current consumption MINI LOGIC SERIES INVERTER (unbuffer) Symbol OUT Conditions 5.5 2.0 = −50 μ 3 4.5 = − 3 GND = − ...
Page 16
... Symbol t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 17
... CMOS low power consumption to achieve ultra high speed operation correspond to LSTTL IC’s. All gates of the internal circuitry have buffered outputs to ensure high noise immunity and output stability. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and V . ...
Page 18
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 18 Environmental code ...
Page 19
... V IH Input voltage “L” level V IL “H” level Output voltage V IN “L” level Input current Current consumption MINI LOGIC SERIES 2 INPUT AND GATE Symbol OUT 0 to 100 ( Conditions V CC 2.0 ⎯ 5 2.0 ⎯ 5.5 2.0 = −50 μ ...
Page 20
... Symbol t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 21
... CMOS low power consumption to achieve ultra high speed operation correspond to LSTTL IC’s. All gates of the internal circuitry have buffered outputs to ensure high noise immunity and output stability. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and V ...
Page 22
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 22 Environmental code ...
Page 23
... V N Hysteresis voltage V H “H” level Output voltage “L” level Input current Current consumption MINI LOGIC SERIES SCHMITT INVERTER Symbol OUT Conditions V CC 3.0 ⎯ 4.5 5.5 3.0 ⎯ 4.5 5.5 3.0 ⎯ 4.5 5.5 2.0 = − ...
Page 24
... Symbol t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 25
... CMOS low power consumption to achieve ultra high speed operation correspond to LSTTL IC’s. All gates of the internal circuitry have buffered outputs to ensure high noise immunity and output stability. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and V ...
Page 26
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 26 Environmental code ...
Page 27
... Symbol “H” level V IH Input voltage “L” level “H” level Output voltage “L” level Input current Current consumption MINI LOGIC SERIES 2 INPUT OR GATE Symbol OUT 0 to 100 ( Conditions V CC 2.0 ⎯ 5 2.0 ⎯ 5.5 2.0 = −50 μ ...
Page 28
... Symbol t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 29
... CMOS low power consumption to achieve ultra high speed operation correspond to LSTTL IC’s. All gates of the internal circuitry have buffered outputs to ensure high noise immunity and output stability. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and V . ...
Page 30
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 30 Environmental code ...
Page 31
... V IH Input voltage “L” level “H” level Output voltage V IN “L” level Input current Current consumption MINI LOGIC SERIES EXCLUSIVE OR GATE Symbol OUT 0 to 100 ( Conditions V CC 2.0 ⎯ 5 2.0 ⎯ 5.5 2.0 = −50 μ ...
Page 32
... Symbol t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 33
... CMOS low power consumption to achieve operation by only a couple of batteries ( V). The internal circuitry has buffered outputs to ensure high noise immunity and output stability. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and V ...
Page 34
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 34 Environmental code ...
Page 35
... V IH Input voltage “L” level “H” level Output voltage “L” level Input current Current consumption MINI LOGIC SERIES 2 INPUT NAND GATE Symbol OUT 0 to 1000 ( 500 ( 400 (V Conditions V CC 1.0 ⎯ 1.5 3.0 1.0 ⎯ 1.5 3.0 1.0 = − ...
Page 36
... THL t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 37
... CMOS low power consumption to achieve operation by only a couple of batteries ( V). The internal circuitry has buffered outputs to ensure high noise immunity and output stability. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and V ...
Page 38
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 38 Environmental code ...
Page 39
... IH Input voltage “L” level V IL “H” level Output voltage V IN “L” level Input current Current consumption MINI LOGIC SERIES 2 INPUT NOR GATE Symbol OUT 0 to 1000 ( 500 ( 400 (V Conditions V CC 1.0 ⎯ 1.5 3.0 1.0 ⎯ 1.5 3.0 1.0 = − ...
Page 40
... THL t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 41
... The S-75L04ANC is an inverter fabricated by utilizing advanced silicon-gate CMOS technology which provides the inherent benefit of CMOS low power consumption to achieve operation by only a couple of batteries ( V). The internal circuitry has buffered outputs to ensure high noise immunity and output stability. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and V . ...
Page 42
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 42 Environmental code ...
Page 43
... Rev.3.0 _00 Recommended Operating Conditions Item Power voltage Input voltage Output voltage Input rise / fall time DC Electrical Characteristics Item Symbol “H” level V IH Input voltage “L” level V IL “H” level Output voltage “L” level Input current Current consumption I ...
Page 44
... THL t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 45
... The S-75LU04ANC is a single packaged inverter without buffer fabricated by utilizing advanced silicon-gate CMOS technology which provides the inherent benefit of CMOS low power consumption to achieve operation by only a couple of batteries ( V). The S-75LU04ANC is suitable for a wide variety of linear circuits. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and This allows for interfaces between power supplies of different voltage, output level conversion from and battery backup applications ...
Page 46
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 46 Environmental code ...
Page 47
... V IH Input voltage “L” level V IL “H” level Output voltage “L” level Input current Current consumption MINI LOGIC SERIES INVERTER (unbuffer) Symbol OUT 0 to 1000 ( 500 ( 400 (V Conditions V CC 1.0 ⎯ 1.5 3.0 1.0 ⎯ 1.5 3 ...
Page 48
... THL t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 49
... CMOS low power consumption to achieve operation by only a couple of batteries ( V). The internal circuitry has buffered outputs to ensure high noise immunity and output stability. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and V ...
Page 50
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 50 Environmental code ...
Page 51
... IH Input voltage “L” level V IL “H” level Output voltage V IN “L” level Input current Current consumption MINI LOGIC SERIES 2 INPUT AND GATE Symbol OUT 0 to 1000 ( 500 ( 400 (V Conditions V CC 1.0 ⎯ 1.5 3.0 1.0 ⎯ 1.5 3.0 1.0 = − ...
Page 52
... THL t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 53
... CMOS low power consumption to achieve operation by only a couple of batteries ( V). The internal circuitry has buffered outputs to ensure high noise immunity and output stability. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and V ...
Page 54
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 54 Environmental code ...
Page 55
... V IL “H” level Output voltage “L” level Hysteresis Voltage V H Input current Current consumption MINI LOGIC SERIES SCHMITT INVERTER Symbol OUT 0 to 1000 ( 500 ( 400 (V Conditions V CC 1.0 ⎯ 1.5 3.0 1.0 ⎯ 1.5 3.0 1.0 = − ...
Page 56
... THL t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 57
... CMOS low power consumption to achieve operation by only a couple of batteries ( V). The internal circuitry has buffered outputs to ensure high noise immunity and output stability. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and V ...
Page 58
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 58 Environmental code ...
Page 59
... V IH Input voltage “L” level “H” level Output voltage “L” level Input current Current consumption MINI LOGIC SERIES 2 INPUT OR GATE Symbol OUT 0 to 1000 ( 500 ( 400 (V Conditions V CC 1.0 ⎯ 1.5 3.0 1.0 ⎯ 1.5 3.0 1.0 = − ...
Page 60
... THL t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 61
... CMOS low power consumption to achieve operation by only a couple of batteries ( V). The internal circuitry has buffered outputs to ensure high noise immunity and output stability. Input voltage is allowed to be applied even if power voltage is not supplied because no diode is inserted between an input pin and V ...
Page 62
... Board size : (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation of Package (When Mounted on Board) 62 Environmental code ...
Page 63
... V IH Input voltage “L” level “H” level Output voltage V IN “L” level Input current Current consumption MINI LOGIC SERIES EXCLUSIVE OR GATE Symbol OUT 0 to 1000 ( 500 ( 400 (V Conditions V CC 1.0 ⎯ 1.5 3.0 1.0 ⎯ 1.5 3.0 1.0 = − ...
Page 64
... THL t PLH Propagation delay time t PHL Input capacitance C IN Equivalent internal capacitance the no-load equivalent capacitance inside the circuitry. Refer to the measurement circuit shown below. PD Current consumption is averaged by the following equation. × V × fin + CC(opr Measurement Circuit VIN PG 50 Ω ...
Page 65
...
Page 66
...
Page 67
...
Page 68
... Seiko Instruments Inc. is strictly prohibited. • The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc. ...