pll2073x Samsung Semiconductor, Inc., pll2073x Datasheet
pll2073x
Related parts for pll2073x
pll2073x Summary of contents
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... PLL2073X GENERAL DESCRIPTION The pll2073x is a Phase-Locked Loop (PLL) frequency synthesizer constructed in CMOS on single monolithic structure. The PLL macro-functions provide frequency multiplication capabilities. The output clock frequency FOUT is related to the input clock frequency FIN by the following equation: S FOUT = (m FIN Where, FOUT is the output clock frequency. FIN is the input clock frequency and s are the values for programmable dividers ...
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... FSPLL FUNCTIONAL BLOCK DIAGRAM FIN Pre-Divider (P) Fvco/M 6b M[7:0] P[5:0] S[1:0] PWD 2 AVDD18D AVSS18D Fin/P UP Phase Frequency Detector DN Main-Divider (M) 8b AVDD18A AVSS18A VABB FILTER Charge Pump Voltage Fvco Vctrl Controlled Oscillator Post-Scaler (S) ( PLL2073X FOUT ...
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... PLL2073X CORE PIN DESCRIPTION Pin Name I/O Type AVDD18D DP AVSS18D DG AVDD18A AP AVSS18A AG VABB AB/DB FIN DI FOUT DO FILTER AO PWD DI P[5:0] DI M[7:0] DI S[1:0] DI I/O Type Abbr. — AI: Analog Input — DI: Digital Input — AO: Analog Output — DO: Digital Output — AB: Analog Bi-direction — DB: Digital Bi-direction — AP: Analog Power — ...
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... FSPLL CORE CONFIGURATION FIN PWD M[7:0] P[5:0] S[1:0] 4 M[7] M[6] M[5] M[4] M[3] M[2] M[1] pll2073x M[0] P[5] P[4] P[3] P[2] P[1] P[0] S[1] S[0] PLL2073X FOUT FILTER ...
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... PLL2073X RECOMMENDED OPERATING CONDITIONS Characteristics Supply voltage differential Operating temperature NOTE strongly recommended that all the supply pins (AVDD18D, AVDD18A) be powered to the same supply voltage to avoid power latch-up. DC ELECTRICAL CHARACTERISTICS Characteristics Operating voltage Digital input voltage high Digital input voltage low ...
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... FUNCTIONAL DESCRIPTION A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference or input signal in frequency as well as in phase. The pll2073x can provide frequency multiplication capabilities, but does not guarantee phase synchronization between FIN and FOUT. In this application, it includes the following basic blocks. ...
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... PLL2073X CORE EVALUATION GUIDE 1. The FOUT should be bypassed for external test. 2. The pll2073x contains loop filter (resistor and capacitor), so the FILTER does not necessarily to be connected to external pin. But it is recommended to connect the FILTER to external pin for calibration of loop performance. 3. You can generate various output frequencies by changing M/P/S setting. There are two methods of controlling divider values. — ...
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... The PLL core should be placed as close as possible to the dedicated loop filter and analog Power and ground pins inadvisable to locate noise-generating signals, such as data buses and high-current outputs, near the PLL I/O cells. Other related I/O signals should be placed near the PLL I/O but do not have any pre-defined placement restriction. 8 PLL2073X ...
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... Pins of the core can be assigned externally(Package Pins) or internally(Internal Ports) depending on design methods. — The term "External" implies that the pins should be assigned externally like power pins. — The term "Internal/External" implies that these pins are user dependent. pll2073x 0.18 m 20MHZ ~ 300MHZ FSPLL FILTER AVDD18A:P VABB:G ...
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... FILTER routing path should not be crossed by any signals and should not run next to digital signals. External loop filter pin should be placed between analog power and ground to avoid stray coupling outside the chip and magnetic coupling via bond wires. Loop filter components should be placed as close as possible. PLL2073X ...
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... PLL2073X FEEDBACK REQUEST Thank you for having an interest in our products. Please fill out this form, especially the items which you want to request. Parameter Process Supply voltage (VDD) Input frequency (FIN) Output frequency (FOUT) Cycle to cycle jitter (TJCC) Period jitter (TJP) Output duty ratio (TOD) ...
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... Long-Term Jitter Long-term jitter is the maximum deviation of output clock’s transition from its ideal position, after many cycles. The term “many” depends on the application and the frequency Ideal Cycle FOUT T T i-1 i TJCC = max(T -T i+1 Cycle 0 Cycle N TJLP TJP T i PLL2073X ...
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... PLL2073X Tracking Jitter Tracking jitter is the maximum deviation of output clock(FOUT)’s transition from input clock (FIN) position. Trigger FIN delay FOUT TJT 0.18 m 20MHZ ~ 300MHZ FSPLL 13 ...