A1240A-1CQ256B ACTEL [Actel Corporation], A1240A-1CQ256B Datasheet

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A1240A-1CQ256B

Manufacturer Part Number
A1240A-1CQ256B
Description
HiRel FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
HiRel FPGAs
Fe a t ur es
• Highly Predictable Performance with 100% Automatic
• Device Sizes from 1,200 to 20,000 Gates
• Up to 6 Fast, Low-Skew Clock Networks
• Up to 202 User-Programmable I/O Pins
• More Than 500 Macro Functions
• Up to 1,276 Dedicated Flip-Flops
• I/O Drive to 10 mA
• Devices Available to DSCC SMD
• CQFP and CPGA Packaging
• Nonvolatile, User Programmable
• Logic Fully Tested Prior to Shipment
• 100% Military Temperature Tested (–55°C to +125°C)
• QML Certified Devices
• Proven Reliability Data Available
• Successful Military/Avionics Supplier for Over 10 Years
A CT 3 Fe at ure s
• Highest-Performance, Highest-Capacity FPGA Family
• System Performance to 60 MHz over Military Temperature
Pr od uc t F am i l y P r o f i l e
J an u a r y 2 0 0 0
© 2000 Actel Corporation
Capacity
Logic Modules
Flip-Flops (Maximum)
User I/Os (Maximum)
Performance
Packages (by Pin Count)
Placement and Routing
System Gates
Logic Gates
SRAM Bits
S-Modules
C-Modules
Decode
System Speed (maximum)
CPGA
CQFP
Device
Family
(more devices on
A32100DX
55 MHz
15,000
10,000
2,048
1,362
700
662
738
152
20
84
3200DX
A32200DX
208, 256
55 MHz
30,000
20,000
2,560
2,414
1,230
1,184
1,276
202
24
page
• Low-Power 0.8µ CMOS Technology
32 0 0D X Fe a t ur es
• 100 MHz System Logic Integration
• Highest Speed FPGA SRAM, up to 2.5 kbits Configurable
• Fast Wide-Decode Circuitry
• Low-Power 0.6µ CMOS Technology
12 0 0X L Fe at ure s
• Pin for Pin Compatible with ACT 2
• System Performance to 50 MHz over Military Temperature
• Low-Power 0.6µ CMOS Technology
A CT 2 Fe at ure s
• Best-Value, High-Capacity FPGA Family
• System Performance to 40 MHz over Military Temperature
• Low-Power 1.0µ CMOS Technology
A CT 1 Fe at ure s
• Lowest-Cost FPGA Family
• System Performance to 20 MHz over Military Temperature
• Low-Power 1.0µ CMOS Technology
2)
Dual-Port SRAM
A1425A
60 MHz
3,750
2,500
310
160
150
435
100
133
132
NA
NA
A1460A
60 MHz
ACT 3
9,000
6,000
848
432
416
976
168
207
196
NA
NA
A14100A
60 MHz
15,000
10,000
1,377
1,493
697
680
228
257
256
NA
NA
A1280XL
1200XL
50 MHz
12,000
8,000
1,232
624
608
998
140
176
172
NA
v 3 . 0
1

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A1240A-1CQ256B Summary of contents

Page 1

HiRel FPGAs • Highly Predictable Performance with 100% Automatic Placement and Routing • Device Sizes from 1,200 to 20,000 Gates • Fast, Low-Skew Clock Networks • 202 User-Programmable I/O Pins ...

Page 2

... Since Actel devices programmed, no downloading from EPROM or SRAM storage is required. Inadvertent erasure is impossible, and there is no need to reload the program after power disruptions. Fabrication using a low-power CMOS process means cooler 2 ACT 2 A1240A A1280A A1010B 6,000 12,000 1,800 4,000 8,000 1,200 NA ...

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Device utilization is typically 95 percent of available logic modules. All Actel devices include on-chip clock drivers and a hard-wired distribution network. User-definable I/Os are capable of driving ...

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A14100 A – 1 Device Revision Part Number A1010 = ...

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... Actel Part Number (Gold Leads) A1010B-PG84B A1010B-1PG84B A1020B-PG84B A1020B-1PG84B A1020B-CQ84B A1020B-1CQ84B A1240A-PG132B A1240A-1PG132B A1280A-PG176B A1280A-1PG176B A1280A-CQ172B A1280A-1CQ172B A1425A-PG133B A1425A-1PG133B A1425A-CQ132B A1425A-1CQ132B A1460A-PG207B A1460A-1PG207B A1460A-CQ196B A1460A-1CQ196B A14100A-PG257B A14100A-1PG257B A14100A-CQ256B ...

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... A1280XL Device 172-pin Ceramic Quad Flat Pack (CQFP) 176-pin Ceramic Pin Grid Array (CPGA A1240A Device 132-pin Ceramic Pin Grid Array (CPGA) A1280A Device 172-pin Ceramic Quad Flat Pack (CQFP) 176-pin Ceramic Pin Grid Array (CPGA) ...

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... Modules Gates A1280XL 1,232 8,000 Gate Array FPGA Logic Equivalent Device Type Modules Gates A1240A 684 4,000 A1280A 1,232 8,000 Gate Array FPGA Logic Equivalent Device Type Modules Gates ...

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Step Screen 1. Internal Visual 2. Temperature Cycling 3. Constant Acceleration 4. Seal a. Fine b. Gross 5. Visual Inspection ...

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Step Screen 2 1. Wafer Lot Acceptance 3 2. Destructive In-Line Bond Pull 3. Internal Visual 4. Serialization 5. Temperature Cycling 6. Constant Acceleration 7. ...

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Free air temperature range Symbol Parameter Supply Voltage CC V Input Voltage –0 Output ...

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The device junction to case thermal characteristic is the junction to ambient air characteristic is characteristics for ...

Page 12

E quiv al ent C apac it ance The power dissipated by a CMOS circuit can be expressed by Equation 1: Power (uW ...

Page 13

... Fix ed Capa cit anc e V alu es for Act (pF Device Type routed_Clk1 A1010B 41 A1020B 69 A1240A 134 A1280A 168 A1280XL 168 A1425A 75 A1460A 165 A14100A 195 A32100DX 178 A32200DX 230 Type Logic modules (m) Input switching (n) Outputs switching (p) First routed array clock loads (q ...

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Input Delays I/O ...

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Input Delays I/O ...

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Input Delays I/O Module INPY IRD1 0.7 ns ...

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Input Delays I/O Module INYL 0.0 ns INH t = 0.4 ns INSU t = 3.7 ns ...

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put B uffer D el ays GND 50% 50 1.5V PAD 1. DLH DHL AC ...

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ip- Fl ops and La tch es ( SUD G, CLK ...

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ip- Fl ops and La tch es (120 0XL /3 200D ...

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Inp ut Bu ffer La tc hes ( and 120 0XL /3 200D X) PAD ...

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A– ...

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3200 Ope rat i on WCLK WD[7:0] WRAD[5:0] WEN BLKEN Note: Identical ...

Page 24

hronous R ead Oper at i on— RDAD[5:0] RD[7:0] 3200 hronous R ead Oper at i on— WEN WD[7:0] ...

Page 25

Cond it ion s, V Parameter Description Logic Module ...

Page 26

Cond it ion s, V Parameter Description Global Clock ...

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Cond it ion s, V Parameter Description 1 Logic ...

Page 28

Cond it ion s, V Parameter Description Input Module ...

Page 29

Cond it ion s, V Parameter Description 1 TTL ...

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Cond it ion s, V Parameter Description 1 Logic ...

Page 31

Cond it ion s, V Parameter Description Input Module ...

Page 32

Cond it ion s, V Parameter Description 1 TTL ...

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Cond it ion s, V Parameter ...

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Cond it ion s, V Parameter ...

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Cond it ion s, V Parameter ...

Page 36

Cond it ion s, V Parameter Description 1 Logic ...

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Cond it ion s, V Parameter Description I/O Module ...

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Cond it ion s, V Parameter Description 1 CMOS ...

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Cond it ion s, V Parameter Description Routed Array ...

Page 40

Cond it ion s, V Parameter Description 1 Logic ...

Page 41

Cond it ion s, V Parameter Description I/O Module ...

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Cond it ion s, V Parameter Description 1 CMOS ...

Page 43

Cond it ion s, V Parameter Description Routed Array ...

Page 44

Cond it ion s, V Parameter Description ...

Page 45

Cond it ion s, V Parameter Description ...

Page 46

Cond it ion s, V Parameter Description ...

Page 47

Cond it ion s, V Parameter Description ...

Page 48

(Wor st - Cas Cond it ion s, V Parameter Description Logic ...

Page 49

(Wor st - Cas Cond it ion s, V Parameter Description Synchronous ...

Page 50

(Wor st - Cas Cond it ion s, V Parameter Description Input ...

Page 51

(Worst-Case Military Conditions, V Parameter Description 1 TTL Output Module Timing t Data to Pad High DLH t ...

Page 52

(Wor st - Cas Cond it ion s, V Parameter Description Logic ...

Page 53

(Wor st - Cas Cond it ion s, V Parameter Description Synchronous ...

Page 54

(Wor st - Cas Cond it ion s, V Parameter Description Input ...

Page 55

(Worst-Case Military Conditions, V Parameter Description 1 TTL Output Module Timing t Data to Pad High DLH t ...

Page 56

CLK Clock (Input) ACT 1 only. TTL Clock input for global clock distribution network. The Clock input is buffered prior to clocking the logic modules. This pin can also be used ...

Page 57

TDI Test Data In Serial data input for JTAG instructions and data. Data is shifted in on the rising edge of TCLK. This pin functions as an I/O when the JTAG fuse is not programmed. JTAG pins are only available ...

Page 58

84 Vie ...

Page 59

A1010B Pin Number Function A1 I/O A2 I/O A3 I/O A4 I/O A5 I/O A6 I/O A7 I/O A8 I/O A9 I/O A10 I/O A11 PRA, I I/O B4 I/O ...

Page 60

132 ew ...

Page 61

... I/O H2 I/O H3 I/O H4 I/O H10 I/O H11 I/O H12 I/O H13 GND J1 I/O J2 GND J3 GND J11 GND J12 I/O J13 I/O K1 I/O K2 I/O K3 I A1240A Pin Number Function I/O K11 I/O K12 GND K13 I/O L1 I/O L2 I/O L3 I/O L4 I/O L5 GND L6 I I/O L9 GND L10 I/O L11 I/O L12 I/O ...

Page 62

133 ew (continued) ...

Page 63

A1425A Pin Number Function GND A3 I/O A4 I/O A5 I/O A6 PRA, I I/O A9 I/O A10 I/O A11 I/O A12 I/O A13 ...

Page 64

176 ew ...

Page 65

A1280A Pin Number Function A1 I/O A2 I/O A3 I/O A4 I/O A5 I/O A6 I/O A7 I/O A8 I/O A9 CLKA, I/O A10 I/O A11 I/O A12 I/O A13 I/O A14 I/O A15 I/O ...

Page 66

ont inu ed) A1280A Pin Number Function H12 GND H13 V CC H14 V CC H15 I/O J1 I/O J2 I J12 GND J13 GND J14 V CC J15 ...

Page 67

207 ew ...

Page 68

A1460A Pin Number Function I/O A4 I/O A5 I/O A6 I/O A7 I/O A8 I/O A9 I/O A10 I/O A11 I/O A12 I/O A13 I/O A14 I/O A15 I/O A16 ...

Page 69

ont inu ed) A1460A Pin Number Function M15 I/O M16 I/O M17 I/O N1 I/O N2 I/O N3 I/O N4 I/O N14 IOPCL, I/O N15 I/O N16 I/O N17 I/O P1 I/O P2 I/O ...

Page 70

257 ew ...

Page 71

A14100A Pin Number Function A1 I/O A2 I/O A3 I/O A4 I/O A5 MODE A6 I/O A7 I/O A8 I/O A9 I/O A10 I/O A11 I/O A12 I/O A13 I/O A14 I/O A15 I/O A16 ...

Page 72

ont inu ed) A14100A Pin Number Function K19 I/O L1 I/O L2 I/O L3 I/O L4 CLKA, I/O L5 CLKB, I/O L15 GND L16 I/O L17 I/O L18 I/O L19 I/O M1 I/O M2 ...

Page 73

84 CQFP ( iew ) Pin #1 Index ...

Page 74

Pi n CQFP A1020B Pin Number Function I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 GND 8 GND 9 I/O 10 I/O 11 I/O 12 I ...

Page 75

132 CQF Vie w) Pin #1 Index ...

Page 76

P in CQF P A1425A Pin Number Function GND 3 SDI, I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 MODE 10 GND I/O 13 I/O 14 I/O 15 ...

Page 77

172 CQF Vie w) 172 171 170 169 168 167 166 165 164 Pin #1 Index ...

Page 78

P in CQF P A1280A Pin Number Function 1 MODE 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 GND 8 I/O 9 I/O 10 I I/O 14 I/O 15 I/O ...

Page 79

P in CQF P (Co nti nue d) A1280A Pin Number Function 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 I/O 96 I/O 97 I/O 98 GND 99 I/O 100 I/O 101 I/O 102 ...

Page 80

196 CQF Vie w) Pin #1 Index ...

Page 81

P in CQF P A1460A Pin Number Function 1 GND 2 SDI, I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 MODE GND 14 I/O 15 ...

Page 82

P in CQF P (Co nti nue d) A1460A Pin Number Function 130 I/O 131 I/O 132 I/O 133 I/O 134 I/O 135 I/O 136 I/O 137 V CC 138 GND 139 GND 140 V CC 141 I/O 142 ...

Page 83

208 CQF Vie w) Pin #1 Index ...

Page 84

P in CQF P A32100DX Pin Number Function 1 GND MODE 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O ...

Page 85

P in CQF P (Co nti nue d) A32100DX Pin Number Function 130 V CC 131 GND 132 V CC 133 V CC 134 I/O 135 I/O 136 V CC 137 I/O 138 I/O 139 I/O 140 I/O 141 ...

Page 86

256 CQF Vie w) Pin #1 Index ...

Page 87

P in CQF P Pin A14100A A32200DX Number Function Function 1 GND NC 2 SDI, I/O GND 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 I/O I/O 10 ...

Page 88

P in CQF P (Co nti nue d) Pin A14100A A32200DX Number Function Function 133 I/O I/O 134 I/O I/O 135 I/O I/O 136 I/O I/O 137 I/O I/O 138 I/O I/O 139 I/O GND 140 I/O I/O 141 ...

Page 89

84 1.100" ...

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132-Pin CPGA 1.360" Orientation ...

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133 1.360" ...

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176 INDEX MARK ...

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207 INDEX MARK 1.77" ...

Page 94

257 Top View 1.970" 0.015" square ...

Page 95

84 CQFP H c Notes: 1. Seal ring and lid are connected to Ground. 2. Lead material is Kovar with ...

Page 96

132-Pin, 172-Pin, 196-Pin, 208-Pin, and 256-Pin CQFP (Cavity Up) Ceramic Tie Bar L1 Notes: 1. Outside leadframe holes (from dimension H) are ...

Page 97

CQFP (Ce ram uad Fla t Pa ck) CQFP 84 Symbol Min. Nom. Max. A 0.070 0.090 0.100 A1 0.060 0.075 0.080 b 0.008 0.010 0.012 c 0.004 0.006 0.008 D1/E1 0.640 0.650 0.660 D2/E2 0.500 BSC ...

Page 98

Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Europe Ltd. Daneshill House, Lutyens Close Basingstoke, Hampshire RG24 8AG United Kingdom Tel: +44-(0)125-630-5600 Fax: +44-(0)125-635-5420 http://www.actel.com Actel Corporation ...

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