nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet
nrf24le1-f16q48-t
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nrf24le1-f16q48-t Summary of contents
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... Ultra-low Power Wireless System On-Chip Solution Preliminary Product Specification v1.1 Key Features • nRF24L01+ 2.4GHz transceiver (250 kbps, 1 Mbps and 2 Mbps air data rates) • Fast microcontroller (8051 compatible) • 16 kbytes program memory (on-chip Flash) • 1 kbyte data memory (on-chip RAM) • ...
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... Preliminary product specification This product specification contains preliminary data; supplementary Product specification Contact details For your nearest dealer, please see Revision 1.1 nRF24LE1 Preliminary Product Specification This product specification contains target specifications for product development. data may be published from Nordic Semiconductor ASA later. This product specification contains final product specifications. Nordic ...
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... Preliminary Product Specification Revision History Date September 2008 Attention! Observe precaution for handling Electrostatic Sensitive Device. HBM (Human Body Model) > 1Kv MM (Machine Model) > 200V Revision 1.1 Version Description 1.1 • Updated ‘Table 76. Pin out map for the 48 pin 7X7mm package’. • ...
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... Preliminary Product Specification Contents 1 Introduction ............................................................................................... 10 1.1 Prerequisites ........................................................................................ 10 1.2 Writing conventions .............................................................................. 10 2 Product overview ...................................................................................... 11 2.1 Features ............................................................................................... 11 2.2 Block diagram ...................................................................................... 13 2.3 Pin assignments ................................................................................... 14 2.3.1 24-pin 4x4 QFN-package variant..................................................... 14 2.3.2 32-pin 5x5 QFN-package variant..................................................... 14 2.3.3 48-pin 7x7 QFN-package variant..................................................... 15 2.4 Pin functions......................................................................................... Transceiver .......................................................................................... 16 3.1 Features ............................................................................................... 16 3.2 Block diagram ...................................................................................... 17 3.3 Functional description .......................................................................... 17 3.3.1 Operational Modes .......................................................................... 17 3.3.2 Air data rate ..................................................................................... 21 3 ...
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... Preliminary Product Specification 4.3 Functional description .......................................................................... 56 4.3.1 Arithmetic Logic Unit (ALU) ............................................................. 56 4.3.2 Instruction set summary .................................................................. 56 4.3.3 Opcode map .................................................................................... 60 5 Memory and I/O organization................................................................... 62 5.1 PDATA memory addressing................................................................. 63 5.2 MCU Special Function Registers ......................................................... 63 5.2.1 Accumulator - ACC ......................................................................... 63 5.2.2 B Register – B ................................................................................. 63 5.2.3 Program Status Word Register - PSW ............................................ 64 5.2.4 Stack Pointer – SP .......................................................................... 64 5.2.5 Data Pointer – ...
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... Preliminary Product Specification 8.5.2 SFR registers................................................................................... 93 9 Interrupts ................................................................................................... 96 9.1 Features ............................................................................................... 96 9.2 Block diagram ...................................................................................... 96 9.3 Functional description .......................................................................... 97 9.4 SFR registers ....................................................................................... 97 9.4.1 Interrupt Enable 0 Register – IEN0.................................................. 98 9.4.2 Interrupt Enable 1 Register – IEN1.................................................. 98 9.4.3 Interrupt Priority Registers – IP0, IP1 .............................................. 98 9.4.4 Interrupt Request Control Registers – IRCON ................................ 99 10 Watchdog .................................................................................................. 100 10.1 Features .............................................................................................. 100 10 ...
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... Preliminary Product Specification 14.3 Functional description ......................................................................... 119 14.4 SFR registers ...................................................................................... 119 14.4.1 Loading the MDx registers .............................................................. 120 14.4.2 Executing calculation ...................................................................... 121 14.4.3 Reading the result from the MDx registers ..................................... 121 14.4.4 Normalizing ..................................................................................... 121 14.4.5 Shifting ............................................................................................ 121 14.4.6 The mdef flag .................................................................................. 121 14.4.7 The mdov flag ................................................................................. 122 15 Encryption/decryption co-processor ..................................................... 123 15 ...
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... Preliminary Product Specification 20.2.1 Recommended use ........................................................................ 154 20.2.2 Master transmitter/receiver ............................................................. 154 20.2.3 Slave transmitter/receiver ............................................................... 155 20.3 SFR registers ...................................................................................... 157 21 ADC ........................................................................................................... 160 21.1 Features .............................................................................................. 160 21.2 Block diagram ..................................................................................... 160 21.3 Functional description ......................................................................... 160 21.3.1 Activation ........................................................................................ 160 21.3.2 Input selection ................................................................................ 161 21.3.3 Reference selection ........................................................................ 161 21.3.4 Resolution ....................................................................................... 161 21.3.5 Conversion modes .......................................................................... 161 21.3.6 Output data coding ......................................................................... 162 21 ...
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... Preliminary Product Specification 29.2.1 Schematics ..................................................................................... 185 29.2.2 Layout ............................................................................................. 186 29.2.3 Bill Of Materials (BOM) ................................................................... 186 29.3 Q24 application example ..................................................................... 187 29.3.1 Schematics ..................................................................................... 187 29.3.2 Layout ............................................................................................. 188 29.3.3 Bill Of Materials (BOM) ................................................................... 188 30 Ordering information ............................................................................... 189 30.1 Package marking ................................................................................ 189 30.1.1 Abbreviations .................................................................................. 189 30.2 Product options ................................................................................... 190 30.2.1 RF silicon ........................................................................................ 190 30.2.2 Development tools .......................................................................... 190 31 Glossary .................................................................................................... 191 Revision 1 ...
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... RF protocols. Benefits of using nRF24LE1 include tighter pro- tocol timing, security, lower power consumption and improved co-existence performance. For the application layer the nRF24LE1 offers a rich set of peripherals including: SPI, 2-wire, UART bit ADC, PWM and an ultra low power analog comparator for voltage level system wake-up. ...
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... Product overview 2.1 Features Features of the nRF24LE1 include: • Fast 8-bit microcontroller: Intel MCS 51 compliant instruction set Reduced instruction cycle time 12x compared to legacy 8051 32 bit multiplication – division unit • Memory: Program memory: 16 kbytes of Flash memory with security features ( erase/ write ...
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... Preliminary Product Specification • Analog comparator: Used as wakeup source Low current consumption (0.75µA typical) Differential or single-ended input Single-ended threshold programmable to 25%, 50%, 75% or 100% of VDD or an arbitrary ref- erence voltage from pin 14-channel input multiplexer Rail-to-rail input voltage range Programmable output polarity • ...
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... Slave M/S Config R80515 OCI Digital Crossbar Retention Latches Pin Crossbar Multi purpose pins - bidir dig/ analog Figure 1. nRF24LE1 block diagram Table 1. below: Reference Chapter 5 on page 62 Chapter 11 on page 102 Chapter 3 on page 16 Chapter 20 on page 154 Chapter 18 on page 142 ...
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... Preliminary Product Specification 2.3 Pin assignments 2.3.1 24-pin 4x4 QFN-package variant Figure 2. nRF24LE1 pin assignment (top view) for a QFN24 4x4 mm package. 2.3.2 32-pin 5x5 QFN-package variant P0.1 VDD DEC1 DEC2 P0.2 PROG P0.3 VSS Figure 3. nRF24LE1 pin assignment (top view) for a QFN32 5x5 mm package. Revision 1 ...
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... Preliminary Product Specification 2.3.3 48-pin 7x7 QFN-package variant P0.1 P0.2 VDD DEC1 DEC2 P0.3 P0.4 P0.5 P0.6 PROG 10 P0.7 11 VSS 12 Figure 4. nRF24LE1 pin assignment (top view) for a QFN48 7x7 mm package. 2.4 Pin functions Name Type VDD Power VSS Power DEC1 Power DEC2 P3.6 – P0.0 Digital or analog I/O PROG Digital Input RESET Digital Input ...
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... RF Transceiver The nRF24LE1 uses the same 2.4GHz GFSK RF transceiver with embedded protocol engine (Enhanced ShockBurst™) that is found in the nRF24L01+ single chip RF Transceiver. The RF Transceiver is designed for operation in the world wide ISM frequency band at 2.400 - 2.4835GHz and is very well suited for ultra low power wireless applications ...
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... Preliminary Product Specification 3.2 Block diagram RF Transmitter TX PA Filter RF Receiver ANT1 RX LNA Filter ANT2 RF Synthesiser Power Management RFCON.rfcken XOSC16M Figure 5. RF Transceiver block diagram 3.3 Functional description This section describes the different operating modes of the RF Transceiver and the parameters used to control it. ...
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... Preliminary Product Specification . Legend: Undefined Undefined Recommended operating mode Possible operating mode Transition state Recommended path between operating modes Possible path between operating modes Pin signal condition Bit state condition PWR_DN = 1 System information TX FIFO empty 3.3.1.2 Power down mode In power down mode the RF Transceiver is disabled with minimal current consumption. All the register val- ues available from the SPI are maintained and the SPI can be activated ...
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... Preliminary Product Specification Standby-II mode In standby-II mode extra clock buffers are active and more current is used compared to standby-I mode. The RF Transceiver enters standby-II mode if the rfce bit is held high on a PTX operation with an empty TX FIFO new packet is downloaded to the TX FIFO, the PLL immediately starts and the packet is transmitted after the normal PLL settling delay (130µ ...
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... Delay from rfce pos. edge to rfcsn low Table 4. Operational timing of RF Transceiver Note: If VDD is turned off the nRF24LE1 enters Deep Sleep or Memory Retention mode, the register values are lost and you must configure the RF Transceiver before entering the modes. ...
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... Preliminary Product Specification 3.3.2 Air data rate The air data rate is the modulated signaling rate the RF Transceiver uses when transmitting and receiving data. It can be 250kbps, 1Mbps or 2Mbps. Using lower air data rate gives better receiver sensitivity than higher air data rate. But, high air data rate gives lower average current consumption and reduced probabil- ity of on-air collisions ...
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... Preliminary Product Specification The PA control is set by the RF_PWR bits in the RF_SETUP register. SPI RF-SETUP (RF_PWR Conditions: VDD = 3.0V, VSS = 0V, T Table 5. RF output power setting for the RF Transceiver 3.3.6 RX/TX control The RX/TX control is set by PRIM_RX bit in the CONFIG register and sets the RF Transceiver in transmit/ receive ...
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... Preliminary Product Specification acknowledgment packet (ACK packet) from the PRX. The PRX can attach user data to the ACK packet enabling a bi-directional data link. The automatic packet transaction handling works as follows: 1. You begin the transaction by transmitting a data packet from the PTX to the PRX. Enhanced ShockBurst™ ...
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... Preliminary Product Specification 3.4.3.3 Packet Control Field Figure 8. shows the format of the 9 bit packet control field, MSB to the left. Payload length 6bit The packet control field contains a 6 bit payload length field bit PID (Packet Identity) field and a 1 bit NO_ACK flag ...
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... Preliminary Product Specification Dynamic Payload Length (DPL alternative to static payload length. DPL enables the transmitter to send packets with variable payload length to the receiver. This means that for a system with different pay- load lengths it is not necessary to scale the packet length to the longest payload. ...
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... Preliminary Product Specification 3.4.4 Automatic packet assembly The automatic packet assembly assembles the preamble, address, packet control field, payload and CRC to make a complete packet before it is transmitted. PID[7:3]= #bytes in TX_FIFO Calculate and add 2 Byte CRC based on Address, PID Revision 1.1 Start: Collect Address from ...
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... Preliminary Product Specification 3.4.5 Automatic packet disassembly After the packet is validated, Enhanced ShockBurst™ disassembles the packet and loads the payload into the RX FIFO, and asserts the RX_DR IRQ. Monitor SETUP_AW wide window of received bit Payload = PID[7:3] bytes from received bit stream ...
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... Preliminary Product Specification 3.4.6 Automatic packet transaction handling Enhanced ShockBurst™ features two functions for automatic packet transaction handling; auto acknowl- edgement and auto re-transmit. 3.4.6.1 Auto Acknowledgement Auto acknowledgment is a function that automatically transmits an ACK packet to the PTX after it has received and validated a packet. The auto acknowledgement function reduces the load of the system MCU and reduces average current consumption ...
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... Preliminary Product Specification • Auto Retransmit Delay (ARD) elapsed. • No address match within 250µs. • After received packet (CRC correct or not) if address match within 250µs. The RF Transceiver asserts the TX_DS IRQ when the ACK packet is received. The RF Transceiver enters standby-I mode if there is no more untransmitted data in the TX FIFO and the rfce bit in the RFCON register is low ...
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... Preliminary Product Specification 3.4.7 Enhanced ShockBurst flowcharts This section contains flowcharts outlining PTX and PRX operation in Enhanced ShockBurst™. 3.4.7.1 PTX operation The flowchart in Figure 12. outlines how a RF Transceiver configured as a PTX behaves after entering standby-I mode. ShockBurst operation Set MAX_RT IRQ Note: ShockBurst™ ...
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... Preliminary Product Specification Activate PTX mode by setting the rfce bit in the RFCON register high. If there is a packet present in the TX FIFO the RF Transceiver enters TX mode and transmits the packet. If Auto Retransmit is enabled, the state machine checks if the NO_ACK flag is set not set, the RF Transceiver enters RX mode to receive an ACK packet ...
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... Preliminary Product Specification 3.4.7.2 PRX operation The flowchart in Figure 13. outlines how a RF Transceiver configured as a PRX behaves after entering standby-I mode. ShockBurst operation Note: ShockBurst™ operation is outlined with a dashed square. Figure 13. PRX operations in Enhanced ShockBurst™ Activate PRX mode by setting the rfce bit in the RFCON register high. The RF Transceiver enters RX mode and starts searching for packets ...
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... Preliminary Product Specification the payload is made available in the RX FIFO and the RX_DR IRQ is asserted. If the last received packet from the transmitter is acknowledged with an ACK packet with payload, the TX_DS IRQ indicates that the PTX received the ACK packet with payload. If the No_ACK flag is not set in the received packet, the PRX enters TX mode ...
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... Preliminary Product Specification • Air data rate • LNA gain The data pipes are enabled with the bits in the EN_RXADDR register. By default only data pipe 0 and 1 are enabled. Each data pipe address is configured in the RX_ADDR_PX registers. Note: Always ensure that none of the data pipes have the same address. ...
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... Preliminary Product Specification The PRX, using MultiCeiver™ and Enhanced ShockBurst™, receives packets from more than one PTX. To ensure that the ACK packet from the PRX is transmitted to the correct PTX, the PRX takes the data pipe address where it received the packet and uses it as the TX address when transmitting the ACK packet. ...
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... Preliminary Product Specification controls the events. Each autonomous mode/sequence ends with a RFIRQ interrupt. All the interrupts are indicated as IRQ events in the timing diagrams. PTX SPI PTX rfce PTX IRQ PTX MODE Standby 1 1 IRQ if No Ack 1Mbps, T IRQ Figure 17 ...
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... Preliminary Product Specification >10us T 130us UL PTX SPI UL PTX rfce PTX IRQ PTX MODE Standby 1 PLL Lock PRX MODE PLL Lock Standby 1 PRX IRQ PRX rfce PRX SPI 130us Figure 18. Timing of Enhanced ShockBurst™ for one packet upload (2Mbps) In Figure 18. ...
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... Preliminary Product Specification In Figure 19. the PTX timing of a packet transmission is shown when the first ACK packet is lost. To see the complete transmission when the ACK packet fails see >10us T 130us UL PTX SPI UL PTX CE PTX IRQ PTX MODE Standby I PLL Lock Figure 19. Timing of Enhanced ShockBurst™ when the first ACK packet is lost (2Mbps) 3 ...
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... Preliminary Product Specification 3.4.10.1 Single transaction with ACK packet and interrupts In Figure 20. the basic auto acknowledgement is shown. After the packet is transmitted by the PTX and received by the PRX the ACK packet is transmitted from the PRX to the PTX. The RX_DR IRQ is asserted after the packet is received by the PRX, whereas the TX_DS IRQ is asserted when the packet is acknowl- edged and the ACK packet is received by the PTX ...
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... Preliminary Product Specification When an address is detected the PTX stays in RX mode until the packet is received. When the retransmit- ted packet is received by the PRX (see back to the PTX. When the ACK is received by the PTX, the TX_DS IRQ is asserted. 3.4.10.3 Single transaction with a lost ACK packet Figure 22 ...
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... Preliminary Product Specification 3.4.10.5 Single transaction with ACK payload packet and lost packet Figure 24 scenario where the first packet is lost and a retransmission is needed before the RX_DR IRQ on the PRX side is asserted. For the PTX both the TX_DS and RX_DR IRQ are asserted after the ACK packet is received ...
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... Preliminary Product Specification 3.4.10.7 Two transactions where max retransmissions is reached MCU PTX UL No address detected. RX off to save current PTX TX:PID=1 PRX RX Packet received. IRQ (PID=1) MCU PRX Radio Turn Around Delay 2 Uploading Paylod for Ack Packet 3 Delay defined by MCU on PTX side, ≥ 130us Figure 26 ...
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... Preliminary Product Specification • The CRC is optional in the ShockBurst™ packet format and is controlled by the EN_CRC bit in the CONFIG register. 3.5 Data and control interface The data and control interface gives you access to all the features in the RF Transceiver. Compared to the standalone component SFR registers are used instead of port pins. Otherwise the interface is identical to the standalone nRF24L01+ chip ...
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... Preliminary Product Specification The RF Transceiver SPI Master is configured through SPIRCON1. Four different sources can generate interrupt, unless they are masked by their respective bits in SPIRCON1. SPIRSTAT reveals which sources that are active. SPIRDAT accesses both the TX (write) and the RX (read) FIFOs, which are two bytes deep. The FIFOs are dynamic and can be refilled according to the state of the status flags: “ ...
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... Preliminary Product Specification Command Command name word (binary) 000A AAAA R_REGISTER 001A AAAA W_REGISTER 0110 0001 R_RX_PAYLOAD 1010 0000 W_TX_PAYLOAD 1110 0001 FLUSH_TX 1110 0010 FLUSH_RX 1110 0011 REUSE_TX_PL 0110 0000 a R_RX_PL_WID a 1010 1PPP W_ACK_PAYLOAD 1011 0000 W_TX_PAYLOAD_NO a ACK 1111 1111 NOP a ...
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... Preliminary Product Specification Note: The 3 bit pipe information in the STATUS register is updated during the RFIRQ high to low transition. The pipe information is unreliable if the STATUS register is read during an RFIRQ high to low transition. 3.5.3 Data FIFO The data FIFOs store transmitted payloads (TX FIFO) or received payloads that are ready to be clocked out (RX FIFO) ...
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... Preliminary Product Specification 3.5.4 Interrupt The RF Transceiver can send interrupts to the MCU. The interrupt (RFIRQ) is activated when TX_DS, RX_DR or MAX_RT are set high by the state machine in the STATUS register. RFIRQ is deactivated when the MCU writes '1' to the interrupt source bit in the STATUS register. The interrupt mask in the CONFIG reg- ister is used to select the IRQ sources that are allowed to activate RFIRQ ...
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... Preliminary Product Specification 3.6 Register map You can configure and control the radio (using read and write commands) by accessing the register map through the SPI. 3.6.1 Register map table All undefined bits in the table below are redundant. They are read out as '0'. ...
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... Preliminary Product Specification Address Mnemonic Bit (Hex) 03 SETUP_AW Reserved 7:2 1 SETUP_RETR 7:4 a ARD 3:0 ARC 05 RF_CH Reserved 7 6:0 RF_CH 06 RF_SETUP 7 CONT_WAVE Reserved 6 5 RF_DR_LOW 4 PLL_LOCK 3 RF_DR_HIGH 2:1 RF_PWR Revision 1.1 Reset Type Value Setup of Address Widths (common for all data pipes) 000000 R/W Only '000000' allowed ...
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... Preliminary Product Specification Address Mnemonic Bit (Hex) Obsolete 0 07 STATUS Reserved 7 6 RX_DR 5 TX_DS 4 MAX_RT 3:1 RX_P_NO 0 TX_FULL 08 OBSERVE_TX 7:4 PLOS_CNT 3:0 ARC_CNT 09 RPD Reserved 7:1 0 RPD 0A 39:0 RX_ADDR_P0 0B 39:0 0xC2C2C RX_ADDR_P1 0C 7:0 RX_ADDR_P2 0D 7:0 RX_ADDR_P3 Revision 1.1 Reset Type Value Don’t care Status Register (In parallel to the SPI command ...
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... Preliminary Product Specification Address Mnemonic Bit (Hex) 0E 7:0 RX_ADDR_P4 0F 7:0 RX_ADDR_P5 10 39:0 TX_ADDR 11 RX_PW_P0 Reserved 7:6 5:0 RX_PW_P0 12 RX_PW_P1 Reserved 7:6 5:0 RX_PW_P1 13 RX_PW_P2 Reserved 7:6 5:0 RX_PW_P2 14 RX_PW_P3 Reserved 7:6 5:0 RX_PW_P3 15 RX_PW_P4 Reserved 7:6 Revision 1.1 Reset Type Value 0xC5 R/W Receive address data pipe 4. Only LSB. MSBytes are equal to RX_ADDR_P139:8 0xC6 R/W Receive address data pipe 5 ...
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... Preliminary Product Specification Address Mnemonic Bit (Hex) 5:0 RX_PW_P4 16 RX_PW_P5 Reserved 7:6 5:0 RX_PW_P5 17 FIFO_STATUS Reserved 7 6 TX_REUSE 5 TX_FULL 4 TX_EMPTY Reserved 3:2 1 RX_FULL 0 RX_EMPTY N/A 255:0 ACK_PLD N/A 255:0 TX_PLD Revision 1.1 Reset Type Value 0 R/W Number of bytes in RX payload in data pipe bytes). 0 Pipe not used byte … ...
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... Preliminary Product Specification Address Mnemonic Bit (Hex) N/A 255:0 RX_PLD 1C DYNPD Reserved 7:6 5 DPL_P5 4 DPL_P4 3 DPL_P3 2 DPL_P2 1 DPL_P1 0 DPL_P0 1D FEATURE Reserved 7:3 2 EN_DPL 1 d EN_ACK_PAY 0 EN_DYN_ACK a. Please take care when setting this parameter. If the ACK payload is more than 15 byte in 2Mbps mode the ARD must be 500µS or more, if the ACK payload is more than 5byte in 1Mbps mode the ARD must be 500µ ...
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... MCU The nRF24LE1 contains a fast 8-bit MCU, which executes the normal 8051 instruction set. The architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Most of the one-byte instructions are performed in a single cycle. The MCU uses one clock per cycle ...
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... Preliminary Product Specification 4.1 Block diagram Memory control Internal PC Flash and DPTR RAM DPTR1 DPS Memory/SFR RAM/SFR control Interface SP ALU ACC MDU MD0 MD2 MD4 MD1 MD3 4.2 Features • Control Unit 8-bit Instruction decoder Reduced instruction cycle time ( times in respect to standard 80C51) • ...
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... ACC or may be driven outside of the unit. The control register, that contains flags such as carry, overflow or parity, is the PSW (Program Status Word) register. The nRF24LE1 also contains an on-chip co-processor MDU (Multiplication Division Unit). This unit enables 32-bit division, 16-bit multiplication, shift and normalize operations, see 4 ...
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... Preliminary Product Specification Mnemonic SUBB A, #data Subtract immediate data from accumulator with borrow INC A Increment accumulator INC Rn Increment register INC direct Increment directly addressed location INC @Ri Increment indirectly addressed location INC DPTR Increment data pointer DEC A Decrement accumulator DEC Rn Decrement register ...
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... Preliminary Product Specification Mnemonic MOV A,Rn Move register to accumulator MOV A,direct Move directly addressed data to accumulator MOV A,@Ri Move indirectly addressed data to accumula- tor MOV A,#data Move immediate data to accumulator MOV Rn,A Move accumulator to register MOV Rn,direct Move directly addressed data to register MOV Rn,#data Move immediate data to register ...
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... Preliminary Product Specification Mnemonic ACALL addr11 Absolute subroutine call LCALL Long subroutine call addr16 RET Return from subroutine RETI Return from interrupt AJMP addr11 Absolute jump LJMP addrl6 Long jump SJMP rel Short jump (relative address) JMP Jump indirect relative to the DPTR ...
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... Preliminary Product Specification 4.3.3 Opcode map Opcode Mnemonic 00H NOP 01H AJMP addr11 02H JUMP addrl6 03H RRA 04H INCA 05H INC direct 06H INC @R0 07H INC @R1 08H INC R0 09H INC R1 0AH INC R2 0BH INC R3 0CH INC R4 0DH INC R5 0EH INC R6 ...
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... Preliminary Product Specification Opcode Mnemonic 32H RETI 33H RLC A 34H ADDC A,#data 35H ADDC A, direct 36H ADDC A,@R0 37H ADDC A,@R1 38H ADDC A,R0 39H ADDC A,R1 3AH ADDC A,R2 3BH ADDC A,R3 3CH ADDC A,R4 3DH ADDC A,R5 3EH ADDC A,R6 3FH ADDC A,R7 40H JC rel 41H AJMP addr11 ...
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... The MCU has 64 Kbytes of separate address space for code and data, an area of 256 byte for internal data (IRAM) and an area of 128 byte for Special Function Registers (SFR). The nRF24LE1 memory blocks has a default setting of 16 Kbytes program memory (flash), 1 Kbytes of data memory (SRAM) and 2 blocks (1 Kbytes standard endurance/512 bytes extended endurance) of non- volatile data memory (flash), see default memory map in sizes can be re-configured based on application needs ...
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... Preliminary Product Specification 5.1 PDATA memory addressing The nRF24LE1 supports PDATA (Paged Data memory) addressing into data space. One page (256 bytes) can be accessed by an indirect addressing scheme through registers R0 and R1 (@R0, @R1). The MPAGE register controls the start address of the PDATA page: ...
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... Preliminary Product Specification 5.2.3 Program Status Word Register - PSW The PSW register contains status bits that reflect the current state of the MCU. Note: The Parity bit can only be modified by hardware upon the state of ACC register. Address Bit Name 0xD0 7 cy Carry flag: Carry bit in arithmetic operations and accumulator for Boolean operations ...
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... Preliminary Product Specification 5.2.6 Data Pointer 1 – DPH1, DPL1 Address 0x84 0x85 Table 25. Data Pointer 1 register (DPH1:DPL1) The Data Pointer Register 1 can be accessed through DPL1 and DPH1. The actual data pointer is selected by DPS register. These registers are intended to hold 16-bit address in the indirect addressing mode used by MOVX (move external memory), MOVC (move program memory) or JMP (computed branch) instructions ...
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... Preliminary Product Specification 5.2.9 Special Function Register Map The map of Special Function Registers is shown in ten. Address X000 X001 0xF8-0xFF FSR FPCR 0xF0-0xF7 B 0xE8-0xEF RFCON MD0 0xE0-0xE7 ACC W2CON1 W2CON0 0xD8-0xDF ADCON W2SADR W2DAT 0xD0-0xD7 PSW ADCCON ADCCON 3 0xC8-0xCF T2CON MPAGE 0xC0-0xC7 ...
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... Preliminary Product Specification 5.2.10 Special Function Registers reset values Reset Register name Address value ACC 0xE0 0x00 Accumulator ADCCON1 0xD3 0x00 ADC Configuration Register 1 ADCCON2 0xD2 0x00 ADC Configuration Register 2 ADCCON3 0xD1 0x00 ADC Configuration Register 3 ADCDATH 0xD4 0x00 ADC Data high byte ...
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... Preliminary Product Specification Reset Register name Address value P0DIR 0x93 0xFF Port 0 pin direction control P1 0x90 0xFF Port 1 value P1CON 0x9F 0x10 Port 1 Configuration Register P1DIR 0x94 0xFF Port 1 pin direction control P2 0xA0 0xFF Port 2 value P2CON 0x97 0x10 Port 2 Configuration Register ...
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... Preliminary Product Specification Reset Register name Address value TL2 0xCC 0x00 Timer 2, low byte TMOD 0x89 0x00 Timer Mode Register W2CON0 0xE2 0x80 2-Wire Configuration Register 0 W2CON1 0xE1 0x00 2-Wire Configuration Register 1/Status Register W2DAT 0xDA 0x00 2-Wire Data Register ...
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... Configurable MCU write protection • Readback protection • HW support for FW upgrades 6.2 Block diagram The Flash block in nRF24LE1 is split in 16k of generic code space memory and 1.5k of Non Volatile data memory. 0xFFFF 0xFC00 0xFBFF NV Data Memory 256 Byte Extended endurance NV Data Memory 256 Byte ...
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... Preliminary Product Specification written a minimum of 20000 times as opposed to 1000 for the ‘normal’ flash based NVM. The different parts of the memory can be accessed by the MCU through normal code and data space operations. Configuration and setup of the memory behavior during normal mode (that is, when MCU is running appli- cation code) is defined by data stored in a separate InfoPage. During the chip reset/start-up sequence the configuration data in the InfoPage is read and stored in the memory configuration SFR’ ...
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... WILL cause changes to device behavior and performance. DSYS - Device System parameters This InfoPage area is used by the nRF24LE1 to store core data like tuning parameters. Erasing and/or changing this area will cause severe changes to device behavior! The operations that can affect this area are SPI commands ERASE ALL, ERASE PAGE and PROGRAM operations to any of these flash addresses with the bit INFEN in register FSR set to logic 1 ...
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... The byte is changed by the RDISMB SPI command and since it cuts the SPI access to the flash main block, must be the last command sent to a nRF24LE1 during flash programming. The only SPI command that can give SPI access to the flash again is ERASE ALL. ...
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... Preliminary Product Specification 6.3.1.2 Memory configuration SFR During the boot sequence the content of the flash InfoPage (IP) is transferred to the memory configuration SFR’s. The same memory configuration SFR’s are used for later interfacing from both SPI and MCU. Address Mnemonic ...
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... During this time the MCU does not respond to any interrupts. Firmware must assure that page erase does not interfere with normal operation of the nRF24LE1. The MCU can perform erase page and write operations to the unprotected part and the data part of the flash main block ...
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... To program the memory a the SPI slave interface is used. SPI slave connection to the flash memory is acti- vated by setting pin PROG = 1 while the reset pin is kept inactive. When the PROG pin is set, selected nRF24LE1 GPIO pins are automatically configured as a SPI slave as shown in Table 32. Further informa- tion on SPI slave timing can be found in chapter 18 on page 142 ...
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... NOTE: a. The InfoPage area DSYS are used to store nRF24LE1 system and tuning parameters. Eras- ing the content of this area WILL cause changes to device behavior and performance. InfoPage area DSYS should ALWAYS be read out and stored prior to using ERASE ALL. Upon completion of the erase the DSYS information must be written back to the flash InfoPage ...
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... Preliminary Product Specification FCSN FSCK FMOSI FMISO FCSN FSCK FMOSI FMISO Figure 34. SPI write operations for direct and addressed commands. Abbreviations Table 34. Flash SPI interface signal abbreviations WREN / WRDIS flash write enable/disable: SPI commands WREN and WRDIS sets and resets the flash write enable latch WEN in register FSR. This latch enables all write and erase operations in the flash blocks ...
Page 79
... Preliminary Product Specification If the FCSN line is kept active after the first data byte is read out the read command can be extended, the address is auto incremented and data continues to shift out. The internal address counter rolls over when the highest address is reached, allowing the complete memory to be read in one continuous read com- mand ...
Page 80
... The command byte command with no data. 6.3.5 Hardware support for firmware upgrade When some of the flash memory is configured as MCU write protected (FPCR.NUPP) and nRF24LE1 is restarted from the protected area, the memory mapping actually changes to make FW upgrades safer. ure 35. shows an example with unprotected and protected area of the flash code space as it will be after programming the flash ...
Page 81
... Preliminary Product Specification 0xFFFF NV Data Memory 0xFA00 0x8000 0x03FF DataNonRetentive DataRetentive 0x0000 Figure 35. Example memory map with 4 kbytes of protected flash program memory After restart address mapping is changed so the protected area now is mapped from address 0x0000 and upwards as shown in Figure 36. ...
Page 82
... Preliminary Product Specification 0xFFFF NV Data Memory 0xFA00 0x83FF DataNonRetentive DataRetentive 0x8000 0x2FFF Program memory 0x0000 Figure 36. Example memory map with 4 kbytes of protected flash program memory The unprotected area is now available in the data space for easy update. Please note that the SRAM blocks in this case is mapped from address 0x8000 independently of MEMCON bit 2 ...
Page 83
... SRAM memory block default located in the XDATA address space from address 0x0000 to 0x03FF. The location of the SRAM blocks in the MCU address space can be changed, see A special feature of the nRF24LE1 SRAM block is that it is composed of two physical 512 byte blocks called DataRetentive (lower 512 bytes) and DataNonRetentive. DataRetentive, in contrast to DataNonRe- ...
Page 84
... Preliminary Product Specification You can address the SRAM memory blocks both as data and code. The MEMCON register controls this behavior: Addr Bit R/W 0xA7 7:3 - Reserved 2 R/W SRAM address location: 0: SRAM blocks start from address 0x0000 1: SRAM blocks start from address 0x8000 1 R/W DataNonRetentive mapping: ...
Page 85
... Preliminary Product Specification 8 Timers/counters The nRF24LE1 contains a set of counters used for timing up important system events. One of the timers (RTC2) is also available in power down mode where it can be used as a wakeup source. 8.1 Features nRF24LE1 includes the following set of timers/counters: • Three 16-bit timers/counters (Timer 0, Timer 1 and Timer 2) which can operate as either a timer with a clock rate based on the MCU clock event counter clocked by signals from the program- mable digital I/O ...
Page 86
... Preliminary Product Specification 8.3 Functional description 8.3.1 Timer 0 and Timer 1 In timer mode, Timer 0/1 is incremented every 12 clock cycles. In the counter mode, the Timer 0/1 is incremented when the falling edge is detected at the corresponding input pin T0 for Timer for Timer 1. Note: Timer input pins T0, T1 and, T2 must be configured as described in Since it takes two clock cycles to recognize a 1-to-0 event, the maximum input count rate is ½ ...
Page 87
... Preliminary Product Specification 8.3.1.2 Mode 2 In this mode, the Timer 0/1 is configured as an 8-bit register with auto reload. /12 Fosc Ti TRi GATE INTi Figure 40. Timer 0 and Timer 1 in mode 2 8.3.1.3 Mode 3 In mode 3 Timer 0/1 is configured as one 8-bit timer/counter and one 8-bit timer, but timer 1 in this mode holds its count ...
Page 88
... Preliminary Product Specification 8.3.2 Timer 2 Timer 2 is controlled by T2CON while the value is in TH2 and TL2. Timer 2 also has four capture and one compare/reload registers which can read a value without pausing or reload a new 16-bit value when Timer 2 reaches zero, see chapter 8.4.7 on page 92 ...
Page 89
... Preliminary Product Specification Timer 2 is incremented every clock cycles depending on the 2:1 prescaler. The prescaler mode is selected by bit t2ps of T2CON register. When t2ps=0, the timer counts up every 12 clock cycles, otherwise every 24 cycles. 8.3.2.3 Event counter mode This mode is invoked by setting the t2i0=0 and t2i1=1 in the T2CON register. ...
Page 90
... Preliminary Product Specification The tf0, tf1 (timer 0 and timer 1 overflow flags), ie0 and ie1 (external interrupt 0 and 1 flags) are automati- cally cleared by hardware when the corresponding service routine is called. 8.4.2 Timer mode register - TMOD TMOD register is used for configuration of Timer 0 and Timer1. ...
Page 91
... Preliminary Product Specification 8.4.5 Timer 2 control register – T2CON T2CON register reflects the current status of Timer 2 and is used to control the Timer 2 operation. Reset Address Bit Name value 0xC8 0x00 7 t2ps Prescaler select. 0: timer 2 is clocked with 1/12 of the ckCpu frequency. 1: timer 2 is clocked with 1/24 of the ckCpu frequency. ...
Page 92
... Preliminary Product Specification 8.4.7 Compare/Capture enable register – CCEN The CCEN register serves as a configuration register for the Compare/Capture Unit associated with the Timer 2. Reset Address Bit value 0xC1 0x00 7:6 5:4 3:2 1:0 8.4.8 Capture registers – CC1, CC2, CC3 The Compare/Capture registers ( CC1 , CC2 , CC3 ) are 16-bit registers used by the Compare/Capture Unit associated with the Timer 2 ...
Page 93
... Preliminary Product Specification 8.4.9 Compare/Reload/Capture register – CRCH, CRCL Address 0xCA 0xCB Table 44. Compare/Reload/Capture register - CRCH, CRCL CRC (Compare/Reload/Capture) register is a 16-bit wide register used by the Compare/Capture Unit asso- ciated with Timer 2. CRCH holds higher byte and CRCL holds lower byte. ...
Page 94
... Preliminary Product Specification Address Name/Mnemonic Bit (Hex) enableExternal- Capture compareMode rtc2Enable 0xB4 rtc2CompareValue 0 RTC2CMP0 0xB5 rtc2CompareValue 1 RTC2CMP1 0xB6 rtc2CaptureValue0 0 RTC2CPT00 0xAB rtc2CaptureValue0 1 RTC2CPT01 0xAC rtc2CaptureValue1 0 RTC2CPT10 Revision 1.1 Reset Type value 3 0 R/W 1: Timer value is captured if required by an IRQ from the Radio (edge detect @ MCU clock). The value is stored in RTC2CPT00 and RTC2CPT01 ...
Page 95
... Preliminary Product Specification Writing or reading RTC2CMP0 and RTC2CMP1: • Disable all interrupts until both registers have been written or read. Reading RTC2CPT00, RTC2CPT01 and RTC2CPT10: • Disable all interrupts until all three registers have been read. Uncertainty in capture values: • 250 ns Revision 1 ...
Page 96
... Preliminary Product Specification 9 Interrupts nRF24LE1 has an advanced interrupt controller with 18 sources, as shown in dynamic program sequencing based upon important real-time events as signalled from timers, the RF Transceiver, pin activity, and so on. 9.1 Features • Interrupt controller with 18 sources and 4 priority levels • Interrupt request flags available • ...
Page 97
... Slave SPI transaction completed Wakeup on pin interrupt Miscellaneous interrupt is the sum of: • XOSC16M started (X16IRQ) • ADC Ready (ADCIRQ) interrupt • RNG ready (RNGIRQ) interrupt Internal Wakeup (from RTC2) interrupt Table 46. nRF24LE1 interrupt sources. section 11.3.1 on page 110 191 106). chapter 8 on page 85. ...
Page 98
... Preliminary Product Specification 9.4.1 Interrupt Enable 0 Register – IEN0 The IEN0 register is responsible for global interrupt system enabling/disabling and also Timer 0, 1 and 2, Port 0 and Serial Port individual interrupts enabling/disabling. Address Bit 0xA8 7 1: Enable interrupts. 0: all interrupts are disabled 6 Not used 5 1: Enable Timer2 (tf2/exf2) interrupt ...
Page 99
... Preliminary Product Specification The contents of the Interrupt Priority registers define the priority levels for each interrupt source according to the tables below. Address Bit 0xA9 7:6 Not used 5:0 Interrupt priority. Each bit together with corresponding bit from IP1 register speci- fies the priority level of the respective interrupt priority group. ...
Page 100
... Preliminary Product Specification 10 Watchdog The on-chip watchdog counter forces a system reset if the running software gets into a hang situation. 10.1 Features • 32 KHz, sub-µA. • 16-bit with an offset of 8 bits. • Minimum Watchdog timeout interval: 7.81 ms. • Maximum Watchdog timeout interval: 512 s. ...
Page 101
... Preliminary Product Specification 10.3 Functional description The following register controls the Watchdog. Address Name/Mnemonic (Hex) 0xAF watchdogStartValue WDSV After a reset, the default state of the Watchdog is disabled. The Watchdog is activated when both bytes in WDSV have been written to LSB first. The watchdog counter then counts down towards 0, and when 0 is reached the complete microcontroller is reset ...
Page 102
... Figure 46. Block diagram of power and clock management 11.2 Modes of operation After nRF24LE1 is reset or powered on it enters active mode and the functional behavior is controlled by software. To enter one of the power saving modes, the PWRDWN register must be written with selected mode (as data). To re-enter the active mode a wakeup source (valid for given power down mode) has to be activated. ...
Page 103
... Preliminary Product Specification The nRF24LE1 modes of operation are summarized in the following table: Mode Deep Sleep Memory retention, timers off Revision 1.1 Brief description Current: See Table 112. on page 179 Powered functions: • pins inclusive wakeup filter Wakeup source(s): From pin Start-up time: • ...
Page 104
... Preliminary Product Specification Mode Memory retention, timers on Register retention Revision 1.1 Brief description Current: See Table 112. on page 179 Powered functions: In addition to Memory retention, timers off: • XOSC32K or RCOSC32K • RTC2 and watchdog clocked on 32 KHz clock Wakeup source(s): From pin, wakeup tick from timer or voltage level on pin (analog ...
Page 105
... Preliminary Product Specification Mode Standby Active Revision 1.1 Brief description Current: See Table 112. on page 179 Powered functions: In addition to Register retention: • Program memory and Data memory • VREG • XOSC16M Wakeup source(s): In addition to Register retention: • The interrupt sources RFIRQ and MISCIRQ (see ...
Page 106
... The clock to the MCU (ckCpu) is sourced from either an on-chip RC oscillator or a crystal oscillator (see chapter 13 on page 115)for details. XOSC16M RCOSC16M SYNTH32K RCOSC32K XOSC32K Revision 1.1 RFCON bit # 2 Clock to RF Tranceiver (ckRF) M Clock to CPU (ckCpu) Clock U Control X CLKCTRL M Clock to RTC2 and Watchdog (CKLF CKLFCTRL Figure 47. nRF24LE1 clock system 106 of 191 ...
Page 107
... Preliminary Product Specification The source and frequency of the clock to the microcontroller system is controlled by the CLKCTRL register: Addr Bit R/W 0xA3 7 R/W 1: Keep XOSC16M on in Register retention mode 6 R/W 1: Clock sourced directly from pin (XC1), bypass oscillators. 0: Clock sourced by XOSC16M or RCOSC16M, see bit 3 5:4 R/W 00: Start both XOSC16M and RCOSC16M ...
Page 108
... Preliminary Product Specification Note source for CLKLF is selected, the MCU system will not start unless CLKLF is operative. For example, when selecting CLKLF from IO pin the external clock must be active for the MCU to wake up by pin from memory retention. 11.3.2 Power down control – PWRDWN ...
Page 109
... Preliminary Product Specification 11.3.3 Operational mode control - OPMCON The OPMCON register is used to control special behavior in some of the operation modes: Addr Bit R/W 0xAE 7:2 - Reserved (always write ‘0’ to these bits) 1 R/W Retention latch control 0: Latch open – pass through 1: Latch locked To keep some internal chip setup, such as pin directions/setup, you need to lock a set of retention latches before entering DeepSleep and memory retention power saving modes ...
Page 110
... Preliminary Product Specification 11.3.5 Wakeup configuration register – WUCON The following wakeup sources is available in STANDBY power down mode. Addr Bit R/W 0xA5 7:6 RW 00: Enable wakeup on RFIRQ if interrupt is enabled (IEN1.1=1) 01: Reserved, not used 10: Enable wakeup on RFIRQ 11: Ignore RFIRQ 5:4 RW 00: Enable wakeup on TICK (from RTC2) if interrupt is enabled (IEN1.5=1) ...
Page 111
... Preliminary Product Specification The function for the WUOPCx registers depends on selected package. The following table shows which port-pin/ gpio that give wakeup if the corresponding enable bit in the WUOPCx register is asserted for each nRF24LE1 package variant. nRF24LE1-Q48 WUOPC bit WUOPC1(7) WUOPC1(6) ...
Page 112
... Preliminary Product Specification 12 Power supply supervisor The power supply supervisor initializes the system at power-on, provides an early warning of impending power failure, and puts the system in reset state if the supply voltage is too low for safe operation. 12.1 Features • Power-on reset with timeout delay • ...
Page 113
... Hysteresis prevents the comparator output from oscillating when VDD is close to threshold. The low-power comparator has a typical threshold voltage of 1 ...
Page 114
... Preliminary Product Specification Use the prog bits to configure the desired threshold voltage (V and 2.7V, defined for falling supply voltage. The comparator has a few tens hysteresis (V Voltage V +V POF HYST V POF 1.8V 12.4 SFR registers Addr Bit Name RW 0xDC 7 enable RW 6:5 prog RW 4 warn ...
Page 115
... On-chip oscillators The nRF24LE1 contains two high frequency oscillators and two low frequency oscillators. The primary high frequency clock source is a 16MHz crystal oscillator. There is also a fast starting 16MHz RC oscillator, which is used primarily to provide the system with a high frequency clock while it is waiting for the crystal oscillator to start up ...
Page 116
... C are stray capacitances on the PCB, while C PCB2 the nRF24LE1 (typically 1pF ensure a functional radio link the frequency accuracy must be ± 60 ppm or better. The initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance must all be taken into account ...
Page 117
... External 16MHz clock The nRF24LE1 may be used with an external 16MHz clock applied to the XC1 pin. Write a ‘1’ to bit 6 in the CLKCTRL register if the external clock is a rail-to-rail digital signal. The input signal may also be analog, coming from e.g. the crystal oscillator of a microcontroller. In this case the crystal oscillator on the nRF24LE1 must also be enabled, since it is used to convert the analog input into a digital clock signal. CLKCTRL 6 must be ‘ ...
Page 118
... External 32kHz clock The nRF24LE1 may be used with an external 32kHz clock applied to the P0.1 port pin. Write ‘100’ to CLKLFCTRL 2:0 if the external clock is a rail-to-rail digital signal, or ‘011’ analog signal coming from e.g. the crystal oscillator of a microcontroller. An analog input signal must have an amplitude of 0.2V peak-to-peak or higher ...
Page 119
... Preliminary Product Specification 14 MDU – Multiply Divide Unit The MDU – Multiplication Division Unit on-chip arithmetic co-processor which enables the MCU to perform additional extended arithmetic operations like 32-bit division, 16-bit multiplication, shift and, nor- malize operations. 14.1 Features The MDU is controlled by the SFR registers MD0 .. MD5 and ARCON . ...
Page 120
... Preliminary Product Specification The ARCON register controls the operation of MDU and informs you about its current state. Address Reset value Bit Name 0xEF 0x00 7 mdef MDU Error flag MDEF. Indicates an improperly performed opera- 6 mdov MDU Overflow flag MDOV. Overflow occurrence in the MDU oper- ...
Page 121
... Preliminary Product Specification 14.4.2 Executing calculation During executing operation, the MDU works on its own in parallel with the MCU. Operation Division 32bit/16bit Division 16bit/16bit Multiplication Shift min. 3 clock cycles (sc = 01h) Normalize min. 4 clock cycles (sc <- 01h) 14.4.3 Reading the result from the MDx registers ...
Page 122
... Preliminary Product Specification The error flag is set when: • If you write to MD0.. MD5 and/or ARCON during phase two of MDU operation (restart or calculations interrupting). • If any of the MDx registers are read during phase two of MDU operation when the error flag mecha- nism is enabled ...
Page 123
... Preliminary Product Specification 15 Encryption/decryption co-processor You can utilize the on-chip encryption/decryption co-processor for more time and power effective firmware. The co-processor Galois Field Multiplier with an 8 bits output. The following polynomial is used: m( This is the polynomial used by AES (Advanced Encryption Standard). ...
Page 124
... Preliminary Product Specification Address Name/Mnemonic (Hex) 0xDF cryptCoProcessor- DataOut CCPDATO Table 71. Encryption/decryption co-processor registers The two registers CCPDATIA and CCPDATIB contain the input data, whilst CCPDATO contains the result from the co-processing. CCPDATO is updated one clock period after one of the input data registers has changed ...
Page 125
... Random number generator The nRF24LE1 contains a true Random Number Generator (RNG), which uses thermal noise to produce a non-deterministic bitstream. A digital corrector algorithm is employed on the bitstream to remove any bias toward ‘1’ or ‘0’. The bits are then queued into an 8-bit register for parallel readout. ...
Page 126
... Preliminary Product Specification 16.4 SFR registers The RNG is interfaced through the two registers; RNGCTL and RNGDAT . RNGCTL contains control bits and a status bit. RNGDAT contains the random data. Addr Bit name 0xD6 7 powerUp 6 correctorEn 5 resultReady 4:0 - Addr Bit name RW 0xD7 7:0 data R Revision 1.1 ...
Page 127
... General purpose IO port and pin assignments The IO pins of the nRF24LE1 are default set to general purpose IO for the MCU. The numbers of available IOs are 7 for the 24 pin 4x4mm, 15 for the 32 pin 5x5mm and 31 for the 48 pin 7x7mm package. The IO pins are also shared with IO requirements from peripheral blocks like SPI and 2 wire as well as more spe- cialized functions like a 32 KHz crystal oscillator and the JTAG interface for the HW debugger ...
Page 128
... Preliminary Product Specification 17.2 Functional description 17.2.1 General purpose IO pin functionality Each of the IO pins on nRF24LE1 has a generic control functionality that sets pin features for the GPIO of the MCU. The features offered by the pins include: • Digital or Analog • Configurable Direction • Configurable Drive Strength • ...
Page 129
... Preliminary Product Specification 17.2.2 PortCrossbar functionality The PortCrossbar sets up connections between the IO pins and the peripheral block of the device. 17.2.2.1 Dynamic allocation of pins The PortCrossbar modifies connections dynamically based on run-time variations in system needs of the peripheral blocks (SPI, 2 wire etc) of the device. This feature is necessary because the number of available pins is small compared to the combined IO needs of all the peripheral blocks ...
Page 130
... Preliminary Product Specification The default pin out also includes connections that are conditionally enabled based on the direction set for the pin. For example, if the P0DIR register in a 24pin 4x4mm package sets pin P0 input, it can be used as a MCU GP input and as the UART receiver. If pin P0.5 is programmed as an output, it can be con- nected to the MCU output, but also have conditional output from the UART/TXD through an AND gate ...
Page 131
... Pin assignments in package 24 pin 4x4 mm The connection map described in this chapter is valid for nRF24LE1 in the 24 pin 4x4 mm package.Pins P0.0 , P0.2 , P0.4 and P0.6 have two system inputs listed per pin. This means that the input from the pin is driving both blocks inputs through an AND gate when the pin is configured as an input. Pin P0.5 and P0 ...
Page 132
... Preliminary Product Specification 17.3.2 Pin assignments in package 32pin 5x5 mm The connection map described in this chapter is valid with the 32-pin 5x5 QFN package. Pins P0.4 to P1.0 have two system inputs listed per pin. This means that the input from the pin is driving both block inputs if the pin is configured as an input ...
Page 133
... Preliminary Product Specification 17.3.3 Pin assignments in package 48 pin 7x7 mm Due to the pin count in this package no IO conflicts exists between digital peripheral blocks. Pins P1.1 - P1.7 have two system inputs listed per pin. This means that the input from the pin is driving both system inputs if the pin is configured as an input ...
Page 134
... Preliminary Product Specification Default Pin connections Inputs Outputs XOSC32K priority 1 P3.6 p3Di 6 p3Do 6 P3.5 p3Di 5 p3Do 5 P3.4 p3Di 4 p3Do 4 P3.3 p3Di 3 p3Do 3 P3.2 p3Di 2 p3Do 2 P3.1 p3Di 1 p3Do 1 P3.0 p3Di 0 p3Do 0 P2.7 p2Di 7 p2Do 7 P2.6 p2Di 6 p2Do 6 P2.5 p2Di 5 p2Do 5 P2.4 p2Di 4 p2Do 4 P2.3 p2Di 3 p2Do 3 P2.2 p2Di 2 p2Do 2 P2.1 p2Di 1 p2Do 1 P2.0 p2Di 0 p2Do 0 P1 ...
Page 135
... Programmable registers Depending on the package size ports are available on nRF24LE1. Desired pin direction and func- tionality is configured using the configuration registers P0DIR , P1DIR , P2DIR , P3DIR , collectively referred to as PxDIR, and P0CON , P1CON , P2CON and P3CON , referred to as PxCON. The PxDIR registers deter- mine the direction of the pins and the PxCON registers contain the functional options for input and output pin operation ...
Page 136
... Preliminary Product Specification Register name: P2DIR Bit Name RW 7:0 dir RW Register name: P3DIR Bit Name RW 7:0 dir RW The input and output options of each pin are configured in the PxCON registers. The PxCON registers have to be written once per pin (one write operation to the PxCON register configures the input/output options of a selected pin in the port) ...
Page 137
... Preliminary Product Specification For instance, to read the output mode of pin P0.5 : Write to P0CON with a bitAddr value of 3'b101, a readAddr value of 1 and a inOut value of 0 (output). Then read from P0CON . The output mode of pin 5 is now found in bits 7:5 of the read data. Register name: P0CON ...
Page 138
... Preliminary Product Specification Register name: P1CON Bit Name RW 7:5 pinMode RW 4 inOut W 3 readAddr W 2:0 bitAddr W Revision 1.1 Address: 0x9F Function Functional input or output mode for pins P1.0 – P1.7. For a write operation: The functional mode you would like to write to the pin. The inOut field determines if the input or output mode is written, the bitAddr field determines which pin is affected ...
Page 139
... Preliminary Product Specification Register name: P2CON Bit Name RW 7:5 pinMode RW 4 inOut W 3 readAddr W 2:0 bitAddr W Revision 1.1 Address: 0x97 Function Functional input or output mode for pins P2.0 – P2.7. (Not used by the 5x5mm package). For a write operation: The functional mode you would like to write to the pin. The inOut field determines if the input or output mode is written, the bitAddr field determines which pin is affected ...
Page 140
... Preliminary Product Specification Register name: P3CON Bit Name RW 7:5 pinMode RW 4 inOut W 3 readAddr W 2:0 bitAddr W Revision 1.1 Address: 0x8F Function Functional input or output mode for pins P3.0 – P3.6. (Not used by the 5x5mm package). For a write operation: The functional mode you would like to write to the pin. The inOut field determines if the input or output mode is written, the bitAddr field determines which pin is affected ...
Page 141
... While the IO ports are used as MCU GPIO, the pin values are read and controlled by the MCU port regis- ters P3 to P0. Address Name 0xB0 P3 0xA0 P2 0x90 P1 0x80 P0 How many ports are available depends on which of the three nRF24LE1 package sizes you are using. Revision 1.1 Bit Reset value 7:0 0xFF R/W 7:0 0xFF R/W 7:0 0xFF ...
Page 142
... Preliminary Product Specification 18 SPI nRF24LE1 features a double buffered Serial Peripheral Interface (SPI). You can configure it to work in all four SPI modes. The default is mode 0. The SPI connects to the following pins of the device: MMISO , MMOSI , MSCK , SCSN , SMISO , SMOSI and SSCK .. ...
Page 143
... Preliminary Product Specification 18.3 Functional description 18.3.1 SPI master The following registers control the SPI master: Address Name/mnemonic Bit (Hex) 0xFC SPIMCON0 clockFrequency dataOrder clockPolarity clockPhase spiMasterEnable 0xFD spiMasterConfig1 SPIMCON1 maskIrqRxFifoFull maskIrqRxDa- taReady maskIrqTxFi- foEmpty Revision 1.1 Reset Type value 6:0 0x02 R/W SPI Master configuration register 0. ...
Page 144
... Preliminary Product Specification Address Name/mnemonic Bit (Hex) maskIrqTxFifo- Ready 0xFE spiMasterStatus SPIMSTAT rxFifoFull rxDataReady txFifoEmpty txFifoReady 0xFF spiMasterData SPIMDAT The SPI Master is configured through SPIMCON0 and SPIMCON1 . It is enabled by setting SPIMCON0.0 to ‘1’. The SPI Master supports all four SPI modes, selected by SPIMCON0.2 and SPIMCON0.1 as described ...
Page 145
... Preliminary Product Specification 18.3.2 SPI slave The following registers control the SPI slave: Address Name/mnemonic Bit (Hex) 0xBC spiSlaveConfig0 SPISCON0 Reserved maskIrqRxDa- taReady Reserved maskIrqTxFifo- Ready dataOrder clockPolarity clockPhase spiSlaveEnable 0xBD Reserved Reserved maskIrqScsnHigh maskIrqScsnLow 0xBE spiSlaveStatus SPISSTAT scsnHigh Revision 1.1 Reset ...
Page 146
... Preliminary Product Specification Address Name/mnemonic Bit (Hex) scsnLow Reserved rxDataReady Reserved Reserved 0XBF spiSlaveData SPISDAT 0xB7 Reserved The SPI slave is configured through SPISCON0 and SPISCON1 . It is enabled by setting SPISCON0.0 to ‘1’. The SPI Slave supports all four SPI modes, selected by SPISCON0.2 and SPISCON0.1 as described ...
Page 147
... Preliminary Product Specification Mode 0: SCK (clockPolarity = ’0') Mode 2: SCK (clockPolarity = ’1') Sample points dataOrder = ’0' Bit # dataOrder = ’1' Figure 60. SPI Modes 0 and 2: clockPhase = ‘0’. One byte transmission. Mode 1: SCK (clockPolarity = ’0') Mode 3: SCK (clockPolarity = ’1') Sample points MOSI MISO dataOrder = ’ ...
Page 148
... Preliminary Product Specification xCSN Tcc xSCK Tdc xMOSI Tcsd xMISO Figure 62. SPI timing diagram. One byte transmission. Revision 1.1 Tch Tch Tcl Tcl Tdh Tcd S7 S0 148 of 191 Tcwh Tcwh Tcch Tcdz ...
Page 149
... Preliminary Product Specification Parameters Data to SCK Setup SCK to Data Hold CSN to Data Valid SCK to Data Valid SCK Low Time SCK High Time SCK Frequency SCK Rise and Fall CSN to SCK Setup SCK to CSN Hold CSN Inactive time CSN to Output High Z Table 89 ...
Page 150
... Preliminary Product Specification 19 Serial port (UART) The MCU system is configured with one serial port that is identical in operation to the standard 8051 serial port (Serial interface 0). The two serial port signals RXD and TXD are available on device pins UART/RSD and UART/TXD The serial port (UART) derives its clock from the MCU clock; ckCpu. See more information ...
Page 151
... Preliminary Product Specification 19.3.1 Serial port 0 control register – S0CON The S0CON register controls the function of Serial Port 0. Reset Address Bit Name value 0x98 0x00 7:6 sm0: sm1 5 sm20 Multiprocessor communication enable 4 ren0 Serial reception enable: 1: Enable Serial Port 0. 3 tb80 Transmitter bit 8. This bit is used while transmitting data through 2 rb80 Received bit 8 ...
Page 152
... Preliminary Product Specification 19.3.2 Serial port 0 data buffer – S0BUF Address 0x99 Writing data to the SOBUF register sets data in serial output buffer and starts the transmission through Serial Port 0. Reading from the S0BUF reads data from the serial receive buffer. 19.3.3 Serial port 0 reload register – S0RELH, S0RELL Serial Port 0 Reload register is used for Serial Port 0 baud rate generation ...
Page 153
... Preliminary Product Specification 19.3.4 Serial port 0 baud rate select register - ADCON The MSB of this register is used by Serial Port 0 for baud rate generation Reset Address Bit Name value 0xD8 0x00 7 bd 6-0 Revision 1.1 Description Serial Port 0 baud rate select (in modes 1 and 3) When 1, additional internal baud rate generator is used, otherwise Timer 1 overflow is used ...
Page 154
... Preliminary Product Specification 20 2-Wire The nRF24LE1 has a single buffered 2-Wire interface. It can be configured to transmit or receive data as master or slave, at two different baud rates. The 2-Wire is not CBUS compatible. The 2 wire interface connects to device pins W2SDA and W2SCL. 20.1 Features • I2C compatible. ...
Page 155
... Preliminary Product Specification 20.2.2.2 RX mode To enter RX mode, MCU must write the address to the Slave it wants the 2-Wire to connect to, to W2DAT. 7:, and write ‘1’ to the direction bit; W2DAT.0. The byte is then transmitted to the Slave(s). If not masked, an interrupt request is asserted on the rising edge of SCL following the last bit in the byte. Simultaneously, the acknowledge from the addressed Slave is stored in W2CON1 ...
Page 156
... Preliminary Product Specification 20.2.3.1 2-Wire timing Symbol Parameter (CK = 16MHz) f System clock frequency System clock period. PERIOD SCL SCL clock period. PE- RIOD t Time from start condition to SCL STA2SCL0 goes ‘low’. t SCL ‘low’ time after start condition. SCL0F t Data setup time before positive edge DSETUP on SCL ...
Page 157
... Preliminary Product Specification SCL SDA 0 IRQ(RX) IRQ(TX) STATUS RX_DATA Figure 66. Interrupt request timing towards MCU START Condition SDA SCL 1 ACK ADDRESS R/W 20.3 SFR registers The following registers control the 2-Wire: Address Name/Mnemonic Bit (Hex) 0xE2 W2CON0 7:0 broadcastEnable Revision 1 t(P2IRQ) ...
Page 158
... Preliminary Product Specification Address Name/Mnemonic Bit (Hex) clockStop xStop xStart clockFrequency 3:2 masterSelect Revision 1.1 Reset Type value 6 0 R/W Slave only: 1: SCL is kept ‘low’ by the slave between byte transfers. This buys the MCU time to read RX data or write TX data mode SCL is released t after TX data has been written to W2DAT ...
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... Preliminary Product Specification Address Name/Mnemonic Bit (Hex) wire2Enable 0xE1 W2CON1 5:0 maskIrq broadcast stop addressMatch ack_n dataReady 0xD9 W2SADR 6:0 0xDA W2DAT 7:0 The 2-Wire is enabled by setting W2CON0.0 to ‘1’. W2CON0.1 decides whether it shall act as Master or Slave. The baudrate is defined by W2CON0. 3:2. Note: The 2-Wire needs a system clock frequency of at least 4 MHz to function correctly in Standard mode ...
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... ADC nRF24LE1 includes a general purpose ADC with input channels, depending on package variant. The ADC contains an internal 1.2V reference, but can also be used with external reference or full scale range equal to VDD. It can be operated in a single step mode with sampling under software control continuous conversion mode with a programmable sampling rate ...
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... Preliminary Product Specification 21.3.2 Input selection The ADC supports external and 2 internal input channels, and can be configured for single ended or differential measurements. Input channel is selected with the chsel bits. Channel (AIN0-AIN13) are external inputs applied through port pins. Channel 14 and 15 are internally generated inputs equal to 1/3 ⋅ ...
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... Preliminary Product Specification By default the ADC is powered down immediately after end of conversion. It can also be configured to enter standby mode after end of conversion, and proceed to a full power-down after a programmable delay. This shortens the wakeup time if a new conversion is initiated before the power-down delay has elapsed ...
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... Preliminary Product Specification The ADCCON3 register contains 3 overflow bits; uflow is set when the ADC is under ranged, oflow is set when the ADC is over ranged, while range is the logical OR of uflow and oflow . 21.3.7 Driving the analog input The analog input pin draws a small current transient each time the internal sampling capacitor is switched to the input at the beginning of the acquisition phase ...
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... Preliminary Product Specification 21.3.8 SFR registers The ADC is interfaced to the MCU through five registers; ADCCON1 , ADCCON2 , ADCCON3 , ADCDATH and ADCDATL . ADCCON1 , ADCCON2 and ADCCON3 contain configuration settings and status bits. The conver- sion result is contained in the ADCDATH and ADCDATL registers. Addr ...
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... Preliminary Product Specification Addr Bit Name RW 1:0 tacq RW Addr Bit Name RW 0xD1 7:6 resol RW 5 rljust RW 4 uflow R 3 oflow R 2 range R 1 Addr Bit Name RW 0xD4 7 Addr Bit Name RW 0xD5 7 rljust resol ADCDATH 7 ADCDATA 5 ADCDATA 7 ADCDATA 9 ADCDATA 11 ...
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... Preliminary Product Specification 22 Analog comparator The analog comparator is used as a wakeup source. It allows a system wakeup to be triggered by the volt- age level of a differential or single ended analog input applied through the port pins. The comparator has very low current consumption, and is operational in the register retention mode and memory retention mode timer on ...
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... Preliminary Product Specification 22.3.3 Reference selection The inverting comparator input can be connected to 25%, 50%, 75% or 100% of either VDD or an arbitrary reference voltage from AIN3 or AIN9. Configure the refscale bits in COMPCON to select scaling factor. To use VDD as a reference, set cmpref to ‘0’. To use an arbitrary reference, set cmpref to ‘1’ and configure refsel in ADCCON1 to choose between AIN3 and AIN9 as input pin for the reference. Note that ‘ ...
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... Preliminary Product Specification 22.3.8 SFR registers The comparator is interfaced through two registers. ADCCON1 configures the multiplexing of external inputs. Other functions are controlled by the COMPCON register. Addr Bit Name RW 0xDB 7 polarity RW Output polarity: 3:2 refscale RW Reference voltage scaling: 1 cmpref RW Reference select: 0 enable RW Enable/disable comparator: Revision 1 ...
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... PWMDC0 Prescaler 23.3 Functional description The nRF24LE1 PWM is a two-channel PWM with a three register interface. The first register, PWMCON , enables the PWM function and sets the PWM period length, which is the number of clock cycles for one PWM period, as shown in Table 106. PWM channel. When one of these registers is written, the corresponding PWM signal changes immedi- ately to the new value. This can result in four transitions within one PWM period, but the transition period will always have a “ ...
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... Preliminary Product Specification PWMCON 7:6 (Number of bits) 00 (5) 01 ( (8) f Table 106. PWM frequency and duty-cycle setting The PWM is controlled by SFR 0xB2, 0XA1 and 0xA2. Addr SFR (HEX) R/W #bit 0xB2 R/W 8 0xA1 R/W 8 0xA2 R/W 8 Revision 1.1 PWM frequency 1 ⋅ ⋅ PWMCON ...
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... Preliminary Product Specification 24 Absolute maximum ratings Maximum ratings are the extreme limits to which the nRF24LE1 can be exposed without permanently dam- aging it. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. The device is not guaranteed to operate properly at the maximum ratings. ...
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... Preliminary Product Specification 25 Operating condition Symbol Parameter VDD Supply voltage t Supply rise time (0V to 1.9V) R_VDD T Operating temperature A a. The on-chip power-on reset circuitry may not function properly for rise times outside the specified inter- val. Revision 1.1 Notes Min. Typ. 1.9 a 1µs -40 Table 109 ...
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... Preliminary Product Specification 26 Electrical specifications This section contains electrical and timing specifications. = − 40ºC to +85ºC (unless otherwise noted) Conditions: VDD = 3.0V Symbol Parameter (condition) V Input high voltage IH V Input low voltage IL V Output high voltage (std. drive, 0.5mA Output high voltage (high-drive, 5mA) ...
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... Preliminary Product Specification Symbol Parameter (condition Adjacent Channel Transmit Power RF1.250 1MHz (250kbps Adjacent Channel Transmit Power RF2.250 2MHz (250kbps) Receiver operation RX Maximum received signal at < 0.1% MAX BER RX Sensitivity (0.1% BER Mbps SENS RX Sensitivity (0.1% BER Mbps SENS RX Sensitivity (0.1% BER) @ 250 kbps SENS RX selectivity according to ETSI EN 300 440-1 V1 ...
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... Preliminary Product Specification Symbol Parameter (condition) C ACS, C/I f > 6MHz (1 Mbps) Nth i C ACS, C/I f > 25MHz (1 Mbps) Nth i C/I C/I co-channel (250 kbps ACS, C/I 1MHz (250 kbps) 1ST C ACS, C/I 2MHz (250 kbps) 2ND C ACS, C/I 3MHz (250 kbps) 3RD C ACS, C/I f > ...
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... Preliminary Product Specification Symbol Parameter (condition) = +25 ° Data retention (T RET A Extended endurance non-volatile data memory T Byte write time PROG T Page erase time ERASE T Mass erase time ME N Endurance ENDUR = +25 ° Data retention (T RET A 16MHz crystal f Nominal frequency (parallel resonant) ...
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... Preliminary Product Specification l. Defined as the deviation of the last code transition (111...110) to (111...111) from the ideal, after correcting for offset error. m. Measured with 100k Ω source resistance and a 330pF bypass capacitor between the analog input and VSS. n. Includes initial accuracy, stability over temperature, aging and frequency pulling due to incorrect load capacitance ...
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... Preliminary Product Specification 26.1 Power consumption Conditions: VDD = 3.0V +25ºC Symbol Parameter (condition) Core functions Deep sleep mode Memory retention mode, timers off Memory retention mode, timers on (CLKLF from XOSC32K) Memory retention mode, timers on (CLKLF from RCOSC32K) Register retention mode (CLKLF from XOSC32K) ...
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... Preliminary Product Specification Symbol Parameter (condition) RF Transceiver during TX settling RF Transceiver in RX mode (2Mbps) RF Transceiver in RX mode (1Mbps) RF Transceiver in RX mode (250kbps) RF Transceiver during RX settling ADC when busy ADC in standby mode ADC in continuous mode @ 2 ksps (average current) Random number generator Analog comparator a. Antenna load impedance = 15 Ω ...
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... Preliminary Product Specification 27 HW debugger support The nRF24LE1 has the following on-chip hardware debug support for a JTAG debugger: • nRFProbe hardware debugger from Nordic Semiconductor. • System Navigator from First Silicon Solutions (www.fs2.com). These debug modules are available on device pins OCITO, OCTMS, OCITDO,OCITDI, OCITCK when enabled in the flash InfoPage ...
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... Preliminary Product Specification 28 Mechanical specifications nRF24LE1 is packaged in three QFN-packages: • QFN244 0.85 mm, 0.5 mm pitch. • QFN32 0.85 mm, 0.5 mm pitch. • QFN48 0.85 mm, 0.5 mm pitch TOP VIEW A A1 SIDE VIEW TOP VIEW A A1 SIDE VIEW Revision 1 ...
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... Preliminary Product Specification TOP VIEW A A1 SIDE VIEW Package A A1 QFN24 0.80 0.00 0.85 0.02 0.90 0.05 QFN32 0.80 0.00 0.85 0.02 0.90 0.05 QFN48 0.80 0.00 0.85 0.02 0.90 0.05 Table 114. QFN24/32/48 dimensions in mm (bold dimension denotes BSC) Revision 1 BOTTOM VIEW A3 Figure 77. QFN 48 pin 7x7mm D2 0.18 2.60 0.20 0.25 4 2.70 0.5 0.30 2.80 0.18 3.20 0.20 0.25 5 3.30 0.5 0.30 3.40 0.18 3.90 0.20 0.25 7 4.00 0.5 0.30 4.10 182 of 191 ...
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... Preliminary Product Specification 29 Application example 29.1 Q48 application example 29.1.1 Schematics 1 VCC_nRF 100nF 100nF 33nF GND GND GND R18 100k VCC_nRF GND GND GND Revision 1.1 C2 15pF X1 16MHz C1 15pF GND VCC_nRF R1 GND 22k P0.1 VDD 35 P0.2 VSS 34 VDD ...
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... Preliminary Product Specification 29.1.2 Layout Top silk screen Top view 29.1.3 Bill Of Materials (BOM) Designator Value C1, C2 15pF C3 2.2nF 1.5p C6 1.0p C7, C9, C11 100nF C8, C10 33nF L1 4.7n L2, L3 3.9n R1 22k R18 100k U1 nRF24LE1F16Q48 QFN48 X1 16MHz Revision 1.1 No components in bottom layer Bottom view Footprint 0402s ...
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... Preliminary Product Specification 29.2 Q32 application example 29.2.1 Schematics VCC_nRF 100nF 100nF 33nF R13 GND GND GND 100k GND GND Revision 1.1 C2 15pF X1 16MHz C1 15pF GND VCC_nRF C11 100nF R1 GND 22k P0.1 VDD 2 23 VDD VSS 3 22 DEC1 ANT2 4 21 DEC2 ...
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... Preliminary Product Specification 29.2.2 Layout Top silk screen Top view 29.2.3 Bill Of Materials (BOM) Designator Value C1, C2 15pF C3 2.2nF 1.5p C6 1.0p C7, C9, C11 100nF C8, C10 33nF L1, L2 6.8n L3 4.7n R1 22k R13 100k U1 nRF24LE1F16Q32 QFN32 X1 16MHz Revision 1.1 No components in bottom layer Bottom view Footprint 0402s ...
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... Preliminary Product Specification 29.3 Q24 application example 29.3.1 Schematics VCC_nRF 100nF 100nF 33nF GND GND GND Revision 1 15pF 16MHz C1 15pF GND VCC_nRF R1 22k P0.1 VDD 2 17 VDD VSS 3 16 DEC1 ANT2 4 15 DEC2 ANT1 PROG 5 14 PROG VDD_PA 6 13 ...
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... Preliminary Product Specification 29.3.2 Layout Top silk screen Top view 29.3.3 Bill Of Materials (BOM) Designator C1 C7, C9, C11 C8, C10 L1 nRF24LE1F16 X1 Revision 1.1 No components Value Footprint 15pF 0402s 2.2nF 0402s NA 0402s 1.5p 0402s NP0 +/-0.1pF, 50V 1.0p 0402s NP0 +/-0.1pF, 50V ...
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... Preliminary Product Specification 30 Ordering information 30.1 Package marking 30.1.1 Abbreviations Abbreviation 24LE1 Product number B Build Code, that is, unique code for production sites, package type and test platform. X "X" grade, that is, Engineering Samples (optional). YY Two digit Year number WW Two digit week number ...
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... RF silicon Ordering code nRF24LE1-F16Q24-T nRF24LE1-F16Q24-R7 nRF24LE1-F16Q24-R nRF24LE1-F16Q24-SAMPLE 4x4mm 24-pin QFN, lead free nRF24LE1-F16Q32-T nRF24LE1-F16Q32-R7 nRF24LE1-F16Q32-R nRF24LE1-F16Q32-SAMPLE 5x5mm 32-pin QFN, lead free nRF24LE1-F16Q48-T nRF24LE1-F16Q48-R7 nRF24LE1-F16Q48-R nRF24LE1-F16Q48-SAMPLE 7x7mm 48-pin QFN, lead free a. Minimum Order Quantity 30.2.2 Development tools Type Number nRF6700 nRFgo Starter Kit ...
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... Preliminary Product Specification 31 Glossary Term ACK Acknowledgement ADC Analog to digital converter ART Auto Re-Transmit BOR Brown-Out Reset CE Chip Enable CLK Clock CRC Cyclic Redundancy Check CSN Chip Select NOT ESB Enhanced ShockBurst™ GFSK Gaussian Frequency Shift Keying IRQ Interrupt Request ...