PLL502-26 PhaseLink (PLL), PLL502-26 Datasheet

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PLL502-26

Manufacturer Part Number
PLL502-26
Description
, Vcxo Plus Audio PLL
Manufacturer
PhaseLink (PLL)
Datasheet
FEATURES
DESCRIPTIONS
The PLL502 -26 is a low cost, high pull-range and
low phase noise VCXO, provi ding less than -135dBc
at 10kHz offset at 27MHz. It also integrates an Au dio
clock phase locked loop ideal for the 8.192MHz,
11.2896MHz and 12.288MHz audio outputs, starting
from an audio reference clock. Its very high pull
range makes it ideal for Digital Video applications,
allowing users to save board space and cost.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Low phase noise 27MHz VCXO ( -135 dBc at
10kHz offset).
Integrated variable capacitors.
Wide pull range (+/- 300 ppm).
Low jitter (RMS): 10ps period.
Integrated audio Phase Locked Loop.
Audio clock output (ideal for 8.192MHz,
11.2896MHz, 12.288MHz) .
27MHz crystal input.
Audio Reference clock input.
3.3V operation.
Available in 16 -Pin SOIC.
REF_Audio
VCON
XOUT
XIN
High Pull-Range VCXO (27MHz) with integrated Audio PLL
VARICAP
XTAL
OSC
10X
PLL
OUT_27MHz
OUT_Audio
Note: * Pins reserved for future DAC integration
OUTPUT RANGE
OUTPUT
GND_VCXO
VCXO
Audio
VDD_VCXO
GND_PLL
VDD_PLL
VCON
XOUT
N/C*
XIN
PIN CONFIGURATION
8.192MHz – 12.288MHz
Preliminary
FREQUENCY RANGE
1
2
3
4
5
6
7
8
27MHz
PLL502-26
16
15
14
13
12
11
10
9
N/C*
GND_27MHz
VDD_Audio
OUT_Audio
GND_Audio
REF_Audio
OUT_27MHz
VDD_27MHz
Rev 09/26/03 Page 1
OUTPUT
CMOS
CMOS
TYPE

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PLL502-26 Summary of contents

Page 1

... VDD_VCXO 3 XIN 4 XOUT 5 VCON 6 GND_VCXO 7 GND_PLL 8 Note: * Pins reserved for future DAC integration OUTPUT RANGE OUTPUT FREQUENCY RANGE VCXO Audio 8.192MHz – 12.288MHz OUT_27MHz OUT_Audio PLL502-26 N/C* 16 GND_27MHz 15 OUT_27MHz 14 VDD_27MHz 13 12 VDD_Audio 11 OUT_Audio 10 GND_Audio 9 REF_Audio OUTPUT TYPE 27MHz CMOS CMOS Rev 09/26/03 Page 1 ...

Page 2

... VDD. +3.3V VDD power supply pin for 27MHz output clock. This pin should be P decoupled separately from other VDD. O 27MHz VCXO output clock. P GND connection for 27MHz output buffer circuitry. SYMBOL PLL502-26 Preliminary Description MIN. MAX 0 0.5 V 0.5 I ...

Page 3

... XIN XTAL C /C < 250 VIN 3.3V 0V VIN 3.3V, -3dB CONDITIONS with capacitive decoupling between VDD and GND. 27MHz @100Hz offset 27MHz @1kHz offset 27MHz @10kHz offset 27MHz @100kHz offset 27MHz @1MHz offset PLL502-26 Preliminary MIN. TYP. MAX. 27 0.65 - 1.5 1.15 3.7 0.5 1 MIN. TYP. MAX. ...

Page 4

... XIN DD Ouput load of 10pF 12mA 12mA 4mA OH At TTL level Human Body Model SYMBOL MIN. F XIN C (xtal PLL502-26 Preliminary MIN. TYP. MAX 3.13* 3.47* 2.4 0.4 V – 0 3.3 3000 TYP. MAX. UNITS 9.5 pF 250 ...

Page 5

... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 SOIC Max. 1.75 0.25 0.51 0.25 10.00 4.00 6.20 1. PART NUMBER PLL502 Marking Package P502-26SC 16SOIC P502-26SC 16SOIC (Tape & Reel) PLL502-26 Preliminary TEMPERATURATURE C=COMMERCIAL PACKAGE TYPE S=SOIC t Rev 09/26/03 Page 5 ...

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