bc41b143a-ds-002pd ETC-unknow, bc41b143a-ds-002pd Datasheet
bc41b143a-ds-002pd
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bc41b143a-ds-002pd Summary of contents
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... I/O Radio RF OUT Baseband DSP MCU XTAL BlueCore4-ROM CSP System Architecture This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd _äìÉ`çêÉ»QJolj=`pm=bao Applications ! Cellular Handsets ! Personal Digital Assistants (PDAs) ! Digital cameras and other high-volume consumer products ...
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... Analogue to Digital Converter .................................................................................................... 39 8.2 RF Transmitter....................................................................................................................................... 39 8.2.1 IQ Modulator .............................................................................................................................. 39 8.2.2 Power Amplifier .......................................................................................................................... 39 8.2.3 Auxiliary DAC ............................................................................................................................. 39 8.3 RF Synthesiser ...................................................................................................................................... 39 8.4 Power Control and Regulation............................................................................................................... 39 8.5 Clock Input and Generation ................................................................................................................... 40 8.6 Baseband and Logic .............................................................................................................................. 40 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Contents Page ...
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... Bus-powered Mode .................................................................................................................... 64 11.5.6 Suspend Current ........................................................................................................................ 65 11.5.7 Detach and Wake-Up Signalling ................................................................................................ 65 11.5.8 USB Driver ................................................................................................................................. 65 11.5.9 USB Compliance........................................................................................................................ 66 11.5.10 USB 2.0 Compatibility .......................................................................................................... 66 11.6 Serial Peripheral Interface ..................................................................................................................... 66 11.6.1 Instruction Cycle......................................................................................................................... 66 11.6.2 Writing to BlueCore4-ROM CSP ................................................................................................ 67 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Contents Page ...
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... Application Schematic................................................................................................................................. 81 13 Package Dimensions ................................................................................................................................... 82 14 Ordering Information ................................................................................................................................... 83 14.1 BlueCore4-ROM CSP............................................................................................................................ 83 15 Contact Information ..................................................................................................................................... 84 16 Document References ................................................................................................................................. 85 Terms and Definitions ........................................................................................................................................ 86 Document History ............................................................................................................................................... 89 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Contents Page ...
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... Figure 11.27: PCM Slave Timing Short Frame Sync............................................................................................. 75 Figure 11.28: Example EEPROM Connection ...................................................................................................... 78 Figure 11.29: Example TXCO Enable OR Function .............................................................................................. 78 Figure 12.1: Application Circuit for CSP Package ................................................................................................. 81 Figure 14.1: BlueCore4-ROM CSP Package Dimensions..................................................................................... 82 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Contents Page ...
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... Equation 11.8: Equivalent Negative Resistance.................................................................................................... 56 Equation 11.9: Baud Rate ..................................................................................................................................... 61 Equation 11.10: PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock........................ 75 Equation 11.11: PCM_SYNC Frequency Relative to PCM_CLK........................................................................... 75 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Contents Page ...
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... While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any errors. CSR’s products are not authorised for use in life-support or safety-critical applications . This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Status Information Page ...
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... Park/Sniff/Hold mode ! Clock Request output to control an external clock source This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Auxiliary Features (continued) ! Device can run in low power modes from an external 32KHz clock signal ! Auto Baud Rate setting for different TCXO ...
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... BlueCore4-ROM CSP Pinout Diagram Figure 3.1: BlueCore4-ROM CSP Package This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Orientation from top of device ...
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... UART_CTS C4 internal pull-down USB_DP B5 Bi-directional USB_DN A6 Bi-directional This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Description Transmitter output/switched receiver input Complement of RF_A Voltage DAC Description For crystal or external clock input Drive for crystal Description Synchronous data output Synchronous data input ...
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... AIO[0] D3 Bi-directional AIO[2] C3 Bi-directional This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Description Reset if low. Input debounced so must be low for >5ms to cause a reset Chip select for Serial Peripheral Interface (SPI), active low SPI clock SPI data input into BlueCore ...
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... VSS_ANA B4 VSS VSS_LO B1 VSS This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Description Regulator input Positive supply for UART ports and AIOs Positive supply for PIO [3:0] and [10:8] Positive supply for all other digital input/output ports, and PIO [7:4] Positive supply for internal digital circuitry ...
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... Supply voltage: VREG_IN Note: (1) Typical figures are given for RF performance between -40°C and +105°C. (2) The device will operate without damage with VREG_IN as high as 5.6V. However the RF performance is not guaranteed above 4.2V. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Minimum -40°C -0.4V -0.4V -0.4V VSS-0.4V Minimum -40° ...
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... Low power mode is entered and exited automatically when the IC enters/leaves Deep Sleep mode (5) Regulator is disabled when VREG_EN is pulled low. It can also be disabled by VREG_IN when it is either open circuit or driven to the same voltage as VDD_ANA This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Minimum Typical 1.70 1.78 ...
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... Input and Tri-State Current with: Strong pull-up Strong pull-down Weak pull-up Weak pull-down I/O pad leakage current C input capacitance I Notes: (1) Current sunk into terminal (2) Current sourced out of terminal This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Minimum Typical -0.4 -0.4 0.7VDD - - VDD-0.2 VDD-0.4 -100 - 0 ...
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... Hysteresis Input/Output Terminal Characteristics (Continued) Auxiliary ADC Resolution Input voltage range (LSB size = VDD_ANA/255) Accuracy INL (Guaranteed monotonic) DNL Offset Gain error Input bandwidth Conversion time Sample rate This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Minimum Typical 3 0.7VDD_USB - -1 1 2.5 - 0.0 - 2.8 - ...
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... High Impedance leakage current Offset (1) Integral non-linearity Settling time (50pF load) Note: (1) Specified for an output voltage between 0.2V and VDD_PIO -0.2V. Output is high impedance when chip is in Deep Sleep mode." This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Minimum Typical - 12.5 14.5 monotonic VSS_PADS -10.0 0.0 VDD_PIO-0 ...
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... CDMA/3G TCXO frequencies of 7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz. (5) Clock input can either be sinusoidal or square wave. If the peaks of the signal are below VSS_ANA or above VDD_ANA a DC blocking capacitor is required between the signal and XTAL_IN. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Minimum Typical 8.0 5.0 6 ...
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... SCO connection HV1 SCO connection HV3 SCO connection HV3 30ms sniff Parked 1.28s beacon Standby Host connection Reset (RESETB low) Note: Conditions: 20°C, 1.80V supply This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Connection UART Rate Type (Kbits/s) - 115.2 - 115.2 Master 115 ...
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... Up to three exceptions are allowed in v2.0+EDR of the Bluetooth specification. BlueCore4-ROM CSP is guaranteed to meet the ACP performance as specified by the Bluetooth specification v2.0+EDR. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Basic Data Rate Temperature = +20°C Min Typ - 5 ...
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... Integrated in 1MHz bandwidth and then normalised to a 1Hz bandwidth. (4) Integrated in 30kHz bandwidth and then normalised to a 1Hz bandwidth. (5) Integrated in 5MHz bandwidth and then normalised to a 1Hz bandwidth. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Basic Data Rate Temperature = +20°C (Continued) Min Typ Max ...
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... Measured at the unbalanced port of the balun. Integrated in 100kHz bandwidth and then normalized to 1Hz. Actual figure is typically below -160dBm/Hz except for peaks of -60dBm at 1.6GHz, -45dBm inband at 2.4GHz and -60dBm at 3.2GHz. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Basic Data Rate Temperature = +20°C Frequency ...
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... Note: (1) 0dBm if f <0.831GHz BLOCKING This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Basic Data Rate Temperature = +20°C (Continued) Min Typ Max ( ...
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... Up to three exceptions are allowed in v2.0+EDR of the Bluetooth specification 5.2.2 Receiver Radio Characteristics VDD = 1.8V Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Basic Data Rate Temperature = -40°C Min Typ - 6 ...
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... Up to three exceptions are allowed in v2.0 + EDR of the Bluetooth specification 5.3.2 Receiver Radio Characteristics VDD = 1.8V Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Basic Data Rate Temperature = -25°C Min Typ - 5 ...
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... Up to three exceptions are allowed in v2.0+EDR of the Bluetooth specification 5.4.2 Receiver Radio Characteristics VDD = 1.8V Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Basic Data Rate Temperature = +85°C Min Typ - 3 ...
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... Up to three exceptions are allowed in v2.0+EDR of the Bluetooth specification 5.5.2 Receiver Radio Characteristics VDD = 1.8V Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Basic Data Rate Temperature = +105°C Min Typ - 2 ...
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... 3MHz o EDR Differential Phase Encoding Notes: (1) BlueCore4-ROM CSP firmware maintains the transmit power to be within the Bluetooth v2.0 + EDR specification limits. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Enhanced Data Rate Temperature = +20C Min Typ Max - 1 ...
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... Up to five exceptions are allowed in Bluetooth v2.0 + EDR specification. BlueCore4-ROM is guaranteed to meet the C/I performance as specified by the Bluetooth v2.0 + EDR specification. (3) Measured 2405MHz, 2441MHz, 2477MHz 0 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Enhanced Data Rate Temperature = +20°C Min Typ Max - ...
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... BlueCore4-ROM CSP firmware maintains the transmit power to be within the Bluetooth v2.0 + EDR specification limits. (2) Class 2 RF transmit power range, Bluetooth v2.0 + EDR specification. (3) Measurement methods are in accordance with the Bluetooth v2.0 + EDR specification. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Enhanced Data Rate Temperature = -40°C Min Typ Max - ...
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... DQPSK (1) Sensitivity at 0.01% BER π/4 DQPSK Maximum received signal at (1) 0.1% BER Notes: (1) Measurement methods are in accordance with the Bluetooth v2.0 + EDR specification This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Enhanced Data Rate Temperature = -40°C Min Typ Max - -89 8DPSK - -79 ...
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... BlueCore4-ROM CSP firmware maintains the transmit power to be within the Bluetooth v2.0 + EDR specification limits. (2) Class 2 RF transmit power range, Bluetooth v2.0 + EDR specification. (3) Measurement methods are in accordance with the Bluetooth v2.0 + EDR specification. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Enhanced Data Rate Temperature = -25°C Min Typ Max - ...
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... DQPSK (1) Sensitivity at 0.01% BER π/4 DQPSK Maximum received signal at (1) 0.1% BER Notes: (1) Measurement methods are in accordance with the Bluetooth v2.0 + EDR specification This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Enhanced Data Rate Temperature = -25°C Min Typ Max - -85 8DPSK - -79 ...
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... Measurement methods are in accordance with the Bluetooth v2.0 + EDR specification. (4) Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Enhanced Data Rate Temperature = +85°C Min Typ ...
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... DQPSK (1) Sensitivity at 0.01% BER π/4 DQPSK Maximum received signal at (1) 0.1% BER Notes: (1) Measurement methods are in accordance with the Bluetooth v2.0 + EDR specification This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Enhanced Data Rate Temperature = +85°C Min Typ Max - -85 8DPSK - -74 ...
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... BlueCore4-ROM CSP firmware maintains the transmit power to be within the Bluetooth v2.0 + EDR specification limits. (2) Class 2 RF transmit power range, Bluetooth v2.0 + EDR specification. (3) Measurement methods are in accordance with the Bluetooth v2.0 + EDR specification. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Enhanced Data Rate Temperature = +105C Min Typ Max - ...
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... Sensitivity at 0.01% BER π/4 DQPSK Maximum received signal at (1) 0.1% BER Notes: (1) Measurement methods are in accordance with the Bluetooth v2.0 + EDR specification This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Radio Characteristics – Enhanced Data Rate Temperature = +105°C Min Typ Max - -85 8DPSK ...
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... VDD_PADS VDD_CORE VDD_ANA VREG_IN VDD_LO XTAL_OUT XTAL_IN VDD_RADIO Figure 7.1: BlueCore4-ROM CSP Device Diagram for CSP Package This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Device Diagram AIO[0] AIO[2] VSS_PADS VSS_DIG VSS_ANA VSS_LO ...
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... EDR. 8.4 Power Control and Regulation BlueCore4-ROM CSP contains one linear 1.8V regulator which may be used to power the 1.8V supplies of the device. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Description of Functional Blocks Page ...
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... Bluetooth stack. 8.6.5 ROM 4Mbits of metal programmable ROM is provided for system firmware implementation. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Description of Functional Blocks Page ...
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... The features are configured in firmware. Since the details of some methods are proprietary (for example Intel WCS) please contact CSR for details. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Description of Functional Blocks ...
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... Adaptive Frequency Hopping (AFH), including classifier ! Faster connection – enhanced inquiry scan (immediate FHS response) ! LMP improvements ! Parameter ranges ! Support of AUX1 packet type This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd HCI LM LC Baseband 48KB RAM MCU USB Host I/ O UART ...
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... Maximum allowed by Bluetooth Specification v2.0 + EDR (2) BlueCore4-ROM CSP supports all combinations of active ACL and SCO channels for both master and slave operation, as specified by the Bluetooth Specification v2.0 + EDR This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd (1) (1) (2) (2) Production Information © Cambridge Silicon Radio Limited 2005 ...
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... Refer to separate documentation for full details of the co-existence schemes that CSR supports. Note: Always refer to the Firmware Release Note for the specific functionality of a particular build. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 CSR Bluetooth Software Stacks ...
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... CSR’s BlueLab and Casira development kits are available to allow the evaluation of the BlueCore4-ROM CSP hardware and software, and as toolkits for developing on-chip and host software. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 ...
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... Consequently, the efficiency is maximised. ! The differential encoding also allows for demodulation without the knowledge of an absolute value for the phase of the RF carrier. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd (1) data rates with minimal disruption to Bits Per Symbol Table 10 ...
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... Nevertheless, since each symbol now represents 3 baseband bits, the actual throughput of the data is 3x when compared with the basic data rate packet. Figure 10.3 illustrates the 8DPSK constellation and Table 10.3 defines the phase encoding. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd ...
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... Table 10.3: 3-Bits Determine Phase Shift Between Consecutive Symbols This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd 011 001 100 101 Production Information © Cambridge Silicon Radio Limited 2005 Enhanced Data Rate 000 Phase Shift 0 π ...
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... Starting from the substrate (chip side), the outputs can each be modelled as an ideal current source in parallel with a lossy resistance and a capacitor. The bond wire can be represented as series inductance LNA _ Figure 11.1: Circuit RF_A and RF_B This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd RF Switch R2 10Ω RF Switch R3 10Ω Production Information © ...
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... Bits [15:8] define a delay, t carrier modulation. In this period an unmodulated carrier is transmitted, which aids interoperability with some other vendor equipment which is not strictly Bluetooth compliant. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd ⎛ ⎛ ⎞ CNTRL _ ...
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... If the external clock is driven through a DC blocking capacitor then maximum allowable amplitude is reduced from VDD_ANA to 800mV pk-pk This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Effect PIO[0], PIO[1] and AUX_DAC are not used to control RF. Power ramping is internal. PIO[0] is high during RX and PIO[1] is high during TX. AUX_DAC is not used ...
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... BlueCore4-ROM CSP as low as possible. BlueCore4-ROM CSP consumes about 2mA of current for the duration of PSKEY_CLOCK_STARTUP_DELAY before activating the firmware. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Figure 11.3: TCXO Clock Accuracy Production Information © Cambridge Silicon Radio Limited 2005 ...
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... Reference Crystal Frequency (MHz) 7.68 14.40 15.36 16.20 16.80 19.20 19.44 19.68 19.80 38. 250kHz +26.00 Default Table 11.3: PS Key Values for CDMA/3G Phone TCXO Frequencies This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd 10.0 15.0 20.0 PSKEY_CLOCK_STARTUP_DELAY PSKEY_ANA_FREQ (Units of 1kHz) Production Information © Cambridge Silicon Radio Limited 2005 Device Terminal Descriptions 25.0 30.0 7680 14400 15360 16200 ...
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... BlueCore4-ROM CSP XTAL_IN input. This reference may be either an external clock or from a crystal connected between XTAL_IN and XTAL_OUT. The external reference clock mode is described in Section 11.2. 11.3.1 XTAL Mode BlueCore4-ROM CSP contains a crystal driver circuit. This operates with an external crystal and capacitors to form a Pierce oscillator. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd ...
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... When viewed from the crystal terminals they trim appear in series so each least significant bit (LSB) increment of frequency trim presents a load across the crystal of 55fF. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd ...
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... BlueCore4-ROM CSP crystal driver circuit is based on a transimpedance amplifier, an equivalent negative resistance can be calculated for it with the following formula in Equation 11.8. > R neg ( ) ( 2 π Equation 11.8: Equivalent Negative Resistance This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd ( ) F − × × pullabilit ppm / ...
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... Conditions 3.4pF centre value trim Crystal C = 2pF o Transconductance setting = 2mA/V Loop gain = This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd 5.5 6.5 7.5 8.5 Load Capacitance (pF) 16 MHz 28 MHz Production Information © Cambridge Silicon Radio Limited 2005 Device Terminal Descriptions 9.5 10.5 11.5 12.5 Page ...
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... Gm Typical Gm Minimum Gm Maximum Figure 11.8: Crystal Driver Transconductance vs. Driver Level Register Setting Note: Drive level is set by PS Key PSKEY_XTAL_LVL. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd BlueCore4-ROM XTAL Driver Characteristics PSKEY_XTAL_LVL Production Information © Cambridge Silicon Radio Limited 2005 ...
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... 5pF (3.9pF plus 1.1 pF stray (Crystal total load capacitance 8.5pF) Note: This is for a specific crystal and load capacitance. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Negative Resistance for 16MHz Crystal 6.0 7.0 8.0 9.0 10.0 11.0 Drive Level Setting Production Information © Cambridge Silicon Radio Limited 2005 Device Terminal Descriptions 12 ...
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... Baud Rate Flow Control Parity Number of Stop Bits Bits per channel Table 11.5: Possible UART Settings This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Minimum Maximum Production Information © Cambridge Silicon Radio Limited 2005 Device Terminal Descriptions Possible Values 1200 Baud (≤2%Error) 9600 Baud (≤ ...
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... This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd t BRK Figure 11.10: Break Signal ). There is no requirement to use these standard values. Any Baud rate PSKEY_UART _BAUD_RATE = Rate . 0 004096 Equation 11.9: Baud Rate ...
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... BlueCore4-ROM CSP the standard UART is supplied by VDD_USB so has signalling levels of 0V and VDD_USB, whereas in the UART bypass mode the signals appear on the PIO[4:7] which are supplied by VDD_PADS. Therefore the signalling levels are 0V and VDD_PADS. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd RESETB UART_TX PIO[4] ...
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... Failure to fit this resistor may result in the design failing to be USB compliant in self-powered mode. The internal pull-up in BlueCore-4 ROM CSP is only suitable for bus-powered USB devices (dongles, for example). This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 ...
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... Excessive noise on the 1.8V supply to the analogue supply pins of BlueCore4-ROM CSP will result in reduced receive sensitivity and a distorted RF transmit signal. Figure 11.13: USB Connections for Bus-Powered Mode Note: USB_ON is shared with BlueCore4-ROM CSP PIO terminals. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd PIO 1.5kΩ 27Ω s ...
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... USB Driver A USB Bluetooth device driver is required to provide a software interface between BlueCore4-ROM CSP and Bluetooth software running on the host computer. Suitable drivers are available from www.csrsupport.com. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Value 22 to 27Ω Impedance matching to USB cable ...
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... This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Hold SPI_CSB high for two SPI_CLK cycles Take SPI_CSB low and clock in the 8-bit command ...
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... BlueCore4-ROM CSP should not be connected in a multi-slave arrangement by simple parallel connection of slave MISO lines. When BlueCore4-ROM CSP is deselected (SPI_CSB = 1), the SPI_MISO line does not float. Instead, BlueCore4-ROM CSP outputs 0 if the processor is running stopped. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Address(A) Data(A) Data(A+1) ...
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... When configured as the Master of the PCM interface, BlueCore4-ROM CSP generates PCM_CLK and PCM_SYNC. BlueCore4-ROM Figure 11.17: BlueCore4-ROM CSP as PCM Interface Master When configured as the Slave of the PCM interface, BlueCore4-ROM accepts PCM_CLK rates up to 2048kHz. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd PCM_OUT PCM_IN PCM_CLK 128/256/512kHz PCM_SYNC ...
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... In Short Frame Sync the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always one clock cycle long. PCM_SYNC PCM_CLK PCM_OUT 1 2 PCM_IN Undefined 1 2 Figure 11.20: Short Frame Sync (Shown with 16-bit Sample) This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd BlueCore4-ROM PCM_OUT PCM_IN PCM_CLK Upto 2048kHz PCM_SYNC 8kHz ...
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... PCM_IN The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. With BlueCore4-ROM CSP in Slave mode, the frequency of PCM_CLK can 4.096MHz. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd ...
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... Additional Features BlueCore4-ROM CSP has a mute facility that forces PCM_OUT Master mode, PCM_SYNC may also be forced to 0 while keeping PCM_CLK running which some CODECS use to control power down. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Sign ...
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... Hold time for PCM_CLK low to PCM_IN invalid hpinclkl Note: (1) Assumes normal system clock operation. Figures will vary during low power modes, when system clock speeds are reduced. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Min 4MHz DDS generation. Selection of frequency is - programmable, see Table 11.11 48MHz DDS generation ...
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... PCM_OUT t supinclkl PCM_IN Figure 11.24: PCM Master Timing Long Frame Sync t dmclksynch PCM_SYNC PCM_CLK PCM_OUT PCM_IN Figure 11.25: PCM Master Timing Short Frame Sync This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd f mlk t mclkh mclkl MSB (LSB) LSB (MSB) t hpinclkl ...
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... PCM_CLK t hsclksynch PCM_SYNC t dpout PCM_OUT MSB (LSB) t supinsclkl PCM_IN MSB (LSB) Figure 11.26: PCM Slave Timing Long Frame Sync This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Table 11.10: PCM Slave Timing f sclk t tsclkl t susclksynch t dsclkhpout LSB (MSB) t hpinsclkl Production Information © Cambridge Silicon Radio Limited 2005 ...
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... The frequency of PCM_SYNC relative to PCM_CLK can be set using following equation: Equation 11.11: PCM_SYNC Frequency Relative to PCM_CLK CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set PSKEY_PCM_LOW_JITTER_CONFIG to This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd f sclk t t sclkh ...
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... LONG_LENGTH_SYNC_EN - MASTER_CLK_RATE ACTIVE_SLOT SAMPLE_FORMAT Table 11.11: PSKEY_PCM_LOW_JITTER_CONFIG Description This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd That is, first slot following sync is active, 13-bit linear voice format, Bit Position Description 0 Set selects Master mode with internal generation of PCM_CLK and PCM_SYNC. 1 selects Slave mode requiring externally generated PCM_CLK and PCM_SYNC ...
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... CSR cannot guarantee that these terminal functions remain the same. Refer to the software release note for the implementation of these PIO lines because they are firmware build specific. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Description Sets PCM_CLK counter limit. ...
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... On reset and up to the time the PIO has been configured, PIO[2] is tri-stated. Therefore, the developer must ensure that the circuitry connected to this pin is pulled via a 470kΩ resistor to the appropriate power rail. This ensures that the TCXO is oscillating at start up. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd 2 C EEPROMS for use with BlueCore. This +1.8V 10nF 2.2kΩ ...
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... High impedance XTAL_IN High impedance, 250kΩ to XTAL_OUT XTAL_OUT High impedance, 250kΩ to XTAL_IN Table 11.13: Pin States of BlueCore4-ROM CSP on Reset This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Device Terminal Descriptions Page ...
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... It is essential that the power rail recovers quickly, so the regulator should have a response time of 20μs or less. See Figure 12.1, the application schematic. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Device Terminal Descriptions ...
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... Application Schematic Figure 12.1: Application Circuit for CSP Package This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Application Schematic Page ...
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... Package Dimensions Figure 13.1: BlueCore4-ROM CSP Package Dimensions This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Package Dimensions Page ...
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... Note: XX denotes firmware type and firmware version status. These are determined on a customer and project basis. Minimum Order Quantity 2kpcs taped and reeled This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Package Shipment Size Method 3.8 x 4.0 x 0.7mm Tape and reel Production Information © ...
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... Korea Tel 3473 2372 Fax : +82 2 3473 2205 e-mail: sales@csr.com To contact a CSR representative This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd CSR Denmark Novi Science Park Niels Jernes Vej 10 9220 Aalborg East Denmark Tel: +45 72 200 380 Fax: +45 96 354 599 e-mail: sales@csr ...
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... Selection EEPROMS for Use with BlueCore EDR RF Test Specification RF Prototyping Specification for Enhanced Data Rate IP BlueCore Power Saving Modes This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Reference v2.0 + EDR, 04 November 2004 v2.0, 27 April 2000 bcore-an-008Pb, 30 September 2003 v2.0.e.2, D07r22, 16 March 2004 v ...
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... Global System for Mobile communications HCI Host Controller Interface HV Header Value I/O Input Output IF Intermediate Frequency IQ Modulation In-Phase and Quadrature Modulation This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Terms and Definitions Page ...
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... Special Interest Group SPI Serial Peripheral Interface SSI Signal Strength Indication TCXO Temperature Controlled Crystal Oscillator TDMA Time Division Multiple Access This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Terms and Definitions Page ...
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... Voltage Controlled Oscillator VFBGA Very Fine Ball Grid Array W-CDMA Wideband Code Division Multiple Access WLAN Wireless Local Area Network This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Terms and Definitions Page ...
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... Product Data Sheet BC41B143A-ds-002Pd September 2005 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Addition of Typical Radio Performance – Basic Data Rate section to Data Book Updated Radio Characteristics – Basic Data Rate and Radio Characteristics – EDR ...