SPI-4 ETC2 [List of Unclassifed Manufacturers], SPI-4 Datasheet

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SPI-4

Manufacturer Part Number
SPI-4
Description
Core w/ FIFOs V1.0 For Altera PLDs
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet

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Features
Standards Compliance
1
supported in AMCC’s Ganges device.
Direct Data Mapping is a raw data mode
OIF SPI-4 Phase 1
AMCC FlexBUS-4
odel
OIF-compliant
(compatible with AMCC FlexBUS-4)
with FIFOs
ATM, Packet Over SONET (POS),
and Direct Data Mapping
Single- and multi-link operation,
scalable from 1 to 16 links.
Programmable per-port bandwidth
allocation
Programmable
programmable almost empty/almost
full thresholds.
Programmable burst size
Automatic link selection in the
Source block based on Source
FIFO threshold and flow control
information.
64-bit data bus width.
Parity
data and control words
Altera’s Atlantic Interface on user’s
side.
Full synchronous design, exceeds:
Clk = 200 MHz
Fully automatic test bench including
driver/monitor.
Easy to use in Mux/Demux and
bridge functions
are
generation/checking
SPI-4
FIFO
1
size
Phase
Standards to Silicon
modes
over
with
1
Benefits
Description
The Optical Interworking Forum’s (OIF) SPI-
4 Phase 1 interface allows the
interconnection of Physical Layer devices to
Link Layer devices in 10Gb/s ATM, POS,
and Ethernet applications. Modelware’s
SPI-4 Phase 1 core performs the interface
functions on both sides of the interface as
shown in Figure 1and Figure 2.
Processor
Figure 1: SPI-4 Phase 1 PHY Layer Application
Layer
PHY
Faster FPGA and ASIC development for
improved time-to-market with FlexBUS-
4 functions
Lower development cost through design
reuse
Available source code licensing for easy
design integration and migration to gate
arrays or ASICs
Ample design flexibility using control
signals and generics/parameters
Verified functionality and standards
compliance
Interface
PluriBus
Control
FIFO(s)
Spi4Rx
Tx
Spi4
Core w/ FIFOs V1.0
FIFO(s)
Spi4Tx
Rx
For Altera PLDs
Status
SPI-4 Phase 1
Product Brief
Line Tx
Line Rx
Data
SPI-4
Data
I/F
June 2001
Layer
Link

Related parts for SPI-4

SPI-4 Summary of contents

Page 1

... Figure 1and Figure 2. Spi4 Tx FIFO(s) PHY Layer PluriBus Interface Processor Spi4Rx Control Figure 1: SPI-4 Phase 1 PHY Layer Application Product Brief SPI-4 Phase 1 For Altera PLDs June 2001 Line Tx Data Spi4Tx Link SPI-4 I/F Layer Line Rx ...

Page 2

... The Spi4Tx block monitors the Source FIFOs fill level and the flow control information received from the opposite side of the SPI-4 interface Source FIFO has data and the flow control information for the corresponding channel indicates that it is ready to accept data, the Spi4Tx block initiates a data transfer from the Source FIFO towards the SPI-4 interface ...

Page 3

... Standards to Silicon Exemplar and Leonardo Spectrum are trademarks of Exemplar Logic, Inc. Product Brief SPI-4 Phase 1 Core w/ FIFOs V1.0 For Altera PLDs June 2001 ...

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