CS4382-KQZR CIRRUS [Cirrus Logic], CS4382-KQZR Datasheet - Page 29

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CS4382-KQZR

Manufacturer Part Number
CS4382-KQZR
Description
114 dB, 192 kHz 8-Channel D/A Converter
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
DS514F2
6.6
6.7
7. CONTROL PORT INTERFACE
The control port is used to load all the internal settings. The operation of the control port may be completely asyn-
chronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The CS4382 has MAP auto increment capability, enabled by the INCR bit in the MAP register, which is the MSB. If
INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment
after each byte is written from register 01h to 08h and then from 09h and 11h, allowing block reads or writes of suc-
cessive registers in two separate sections (the counter will not auto-increment to register 09h from register 08h).
When in Stand-Alone Mode, only the “fast” roll-off filter is available.
Filter specifications can be found in Section 1, and filter response plots can be found in Figures
Clock Source Selection
The CS4382 has two serial clock and two left/right clock inputs. The SDINxCLK bits in the control port allow
the user to set which SCLK/LRCK pair is used to latch the data for each SDINx pin. The clocks applied to
LRCK1 and LRCK2 must be derived from the same MCLK and must be exact frequency multiples of each
other as specified in the
SCLK2/LRCK2, if either SCLK/LRCK pair loses synchronization then both SCLK/LRCK pairs will go through
a retime period where the device is re-evaluating clock ratios. During the retime period all DAC pairs are
temporarily inactive, outputs are muted, and the mute control pins will go active according to the MUTEC
register.
If unused, SCLK2 and LRCK2 should be tied static low and SDINx bits should all be set to SCLK1/LRCK1.
In Stand-Alone Mode, all DAC pairs use SCLK1 and LRCK1 for timing and SCLK2/LRCK2 should be tied
to ground.
Using DSD Mode
In Stand-Alone Mode, DSD operation is selected by holding DSD_EN(LRCK1) high and applying the DSD
data and clocks to the appropriate pins. The M2:0 pins set the expected DSD rate and MCLK ratio.
In Control Port Mode, the FM bits set the device into DSD Mode (DSD_EN pin is not required to be held
high). The DIF register then controls the expected DSD rate and MCLK ratio. To access the full range of
DSD clocking modes (other than 64x DSD 4x MCLK and 128x DSD 2x MCLK) the following additional reg-
ister sequence needs to be written:
99h to register 00h
80h to register 1Ah
00h to register 00h
When exiting DSD Mode the following additional sequence needs to be written:
99h to register 00h
00h to register 1Ah
00h to register 00h
During DSD operation, the PCM related pins should either be tied low or remain active with clocks (except
LRCK1 in Stand-Alone Mode). When the DSD related pins are not being used they should either be tied
static low, or remain active with clocks (except M3 in Stand-Alone Mode).
“Switching Characteristics” on page
9. When using both SCLK1/LRCK1 and
CS4382
9
to 32.
29

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