CS4382A-EQZ CIRRUS [Cirrus Logic], CS4382A-EQZ Datasheet - Page 20

• Manufacturer Part Number: CS4382A-EQZ
• Description: 114 dB, 192 kHz 8-channel D/A Converter
• Manufacturer: CIRRUS [Cirrus Logic]

20
3. APPLICATIONS
The CS4382A serially accepts twos complement formatted PCM data at standard audio sample rates including 48,
44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via
the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input
on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer.
The CS4382A can be configured in hardware mode by the M0, M1, M2 , M3 and DSD_EN pins and in software
mode through I
3.1
3.2
(sample-rate range)
Note: These modes are only available in software mode by setting the MCLKDIV bit = 1.
(100 to 200 kHz)
(50 to 100 kHz)
Double-Speed
Single-Speed
Speed Mode
(4 to 50 kHz)
Quad-Speed
Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequen-
cy at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected
automatically during the initialization sequence by counting the number of MCLK transitions during a single
LRCK period. Internal dividers are then set to generate the proper internal clocks. Table 1 illustrates several
standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no re-
quired phase relationship, but MCLK, LRCK and SCLK must be synchronous.
Mode Select
In hardware mode operation is determined by the Mode Select pins. The state of these pins are continually
scanned for any changes. These pins require connection to supply or ground as outlined in figure 6. For
M0, M1, M2 supply is VLC and for M3 and DSD_EN supply is VLS. Tables 2 - 4 show the decode of these
pins.
In software mode the operational mode and data format are set in the FM and DIF registers.
Definitions” on page 41.
MCLK Ratio
MCLK Ratio
MCLK Ratio
2
C or SPI.
Sample
176.4
(kHz)
Rate
44.1
88.2
192
32
48
64
96
Table 1. Common Clock Frequencies
12.2880
12.2880
12.2880
11.2896
11.2896
11.2896
8.1920
8.1920
256x
128x
64x
12.2880
16.9344
18.4320
12.2880
16.9344
18.4320
16.9344
18.4320
384x
192x
96x
MCLK (MHz)
16.3840
22.5792
24.5760
16.3840
22.5792
24.5760
22.5792
24.5760
512x
256x
128x
24.5760
33.8688
36.8640
24.5760
33.8688
36.8640
33.8688
36.8640
768x
384x
192x
mode only
Software
CS4382A
32.7680
45.1584
49.1520
32.7680
45.1584
49.1520
45.1584
49.1520
1024x*
512x*
256x*
“Parameter
DS618PP1