CS4382A-EQZ CIRRUS [Cirrus Logic], CS4382A-EQZ Datasheet - Page 23

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CS4382A-EQZ

Manufacturer Part Number
CS4382A-EQZ
Description
114 dB, 192 kHz 8-channel D/A Converter
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
DS618PP1
3.4
3.5
3.6
SDINx
SDINx
LRCK
SCLK
LRCK
SCLK
1 0
1 0
Oversampling Modes
The CS4382A operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the DSD_EN, M3 and M2 pins in hardware mode or the FM bits in software mode. Single-
Speed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed
mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-speed mode
supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS4382A incorpo-
rates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available
in each of Single, Double, and Quad-Speed modes. These filters have been designed to accommodate a
variety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the “Param-
eter Definitions” on page 41 for more details).
When in hardware mode, only the “fast” roll-off filter is available.
Filter specifications can be found in Section 2, and filter response plots can be found in Figures 19 to 42.
De-Emphasis
The CS4382A includes on-chip digital de-emphasis filters. The de-emphasis feature is included to accom-
modate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction. Figure
13 shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale proportion-
ally with changes in sample rate, Fs if the input sample rate does not match the coefficient which has been
selected.
19 18
17 16
17 16
15 14 13 12 11 10
15 14 13 12 11 10
Left Channel
32 clocks
Left Channel
32 clocks
Figure 11. Format 4 - Right-Justified 20-bit Data
Figure 12. Format 5 - Right-Justified 18-bit Data
9 8 7
9 8 7
6 5 4 3 2 1 0
6 5 4 3 2 1 0
19 18
17 16
17 16
15 14 13 12 11 10
15 14 13 12 11 10
Right Channel
Right Channel
9 8 7
9 8 7
6 5 4 3 2 1 0
6 5 4 3 2 1 0
CS4382A
23

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